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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 61-66
This paper formulates the logic level circuit optimization problem for topological quantum computation. Observing the properties of brading operations in topological quantum computation, we formulate our problem as to find a good gate order and a good initial qubit order. For the problem, we propose an efficient method by utilizing an algorithm for clique finding. Our experimental result shows the effectiveness of our proposed method.
Logic gates, Quantum computing, Integrated circuit modeling, Computational modeling, Circuit synthesis, Circuit optimization, qubit order, quantum circuit, optimization problem, topological quantum computation

S. Yamashita, "An Optimization Problem for Topological Quantum Computation," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 61-66.
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