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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 50-54
Quantum algorithms can be written down in several forms, one of the most common is the quantum circuit representation using discrete gates. The challenge in assessing the computational cost then becomes counting those gates, with realistic costs assigned to each gate. Moreover, interacting pairs of qubits inside most quantum computers will require moving qubits. In many architectures, this will involve cellular automaton-like swapping of qubits. In general, the depth will be described in number of quantum error correction (QEC) cycles, while the total cost will be space-time ``volume'' consisting of the number of qubits involved over that set of QEC cycles. This implies that accurate estimates can be made only in the context of a particular architecture and error correction mechanism.
Logic gates, Quantum computing, Computers, Error correction, Computer architecture, Photonics, Physics, optimization, quantum computation, compilation

R. Van Meter, "Counting Gates, Moving Qubits: Evaluating the Execution Cost of Quantum Circuits," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 50-54.
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