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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 49
Ilia Polian , University of Passau, Germany
ABSTRACT
Summary form only given. This special session will introduce the field to the design automation and test community, focusing on recent developments. The ultimate objective of the session is to initiate a dialogue with quantum informatics community by identifying open problems from quantum informatics which can be tackled by design automation methods such as synthesis, optimisation and verification. Among the four speakers are physicists as well as design automation researchers already working on problems from the quantum informatics domain. The first talk of the session will be given by Professor Rodney Van Meter of Keio University, Fujisawa. He will introduce quantum circuits, focusing on the non-trivial aspects of estimating the implementation cost of a given quantum circuit. Such metrics, which roughly correspond to the circuit’s area in the classical domain, will be of highest importance for any quantum circuit optimisation algorithm. Professor Simon Devitt of the National Institute of Informatics, Tokyo, will introduce the concept of topological quantum computing, which is the foundation of most recent scalable quantum circuit implementations. The third speaker, Professor Shigeru Yamashita of Ritsumeikan University, Shiga, will present his recent results on circuit-level optimisation of topological quantum circuits. The problem instances are mapped to a graph, and the optimisation is performed by identifying maximal cliques in this graph. Finally, Professor Austin Fowler of University of Melbourne will speak on recent developments in quantum error correcting codes and classical challenges that arise in this domain. The first three presentations have accompanying papers that are included in the proceedings.
INDEX TERMS
CITATION

I. Polian, "Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 49.
doi:10.1109/ATS.2012.88
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