2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.13
Leakage test has been a challenge for TSVs in a 3D IC. Most existing methods are still inadequate in terms of the range of leakage currents they can test. In this work, we borrow the wisdom of the IO pin leakage test while enhancing it with two features: (1) we make it more suitable for TSVs which has a much smaller capacitance than an IO pin, and (2) we support leakage binning in a wide range of currents from 1 uA to 128 uA, and thereby allowing flexible test threshold settings and leakage characterization. Since we use only logic gates in the Design-for-Testability circuit, it is also easier to be integrated into the TSV design flow than previous methods.
Through-silicon vias, Delay, Circuit faults, Leakage current, Capacitance, Logic gates, Delay lines, Leakage Binning, 3D IC, Through-Silicon Via, Leakage Test, Design for Testability
Y. Lin, S. Huang, K. (. Tsai and W. Cheng, "Programmable Leakage Test and Binning for TSVs," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 43-48.