The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 37-42
With technology scaling towards smaller geometries, the power density of modern integrated circuits (ICs) can potentially result into high temperatures during test, a problem further compounded by stacking dies in 3D stacked structures (3DSICs). Scheduling tests in a way to minimize the total test time becomes a key issue when temperature constraints are involved, since a more compact schedule leads to a hotter device. Unfortunately, many previous attempts at temperature-bounded scheduling either use inferior temperature models leading to under compaction, or they can only be applied to traditional single-die designs. Simple thermal models based on steady state temperatures are inadequate to schedule tests in 3DSICs due to their limitations. This paper proposes two formulations for test scheduling under thermal constraints for 3DSICs using the superposition principle, which allows for accurate thermal modeling and superior test compaction. This paper then compares them to previous formulations which use steady-state models, and also discusses the inherent limitations of the steady-state model. Results of the algorithms proposed in this paper show the superiority of the schedules obtained for testing 3DSICs.
Steady-state, Schedules, Computational modeling, Benchmark testing, Integrated circuit modeling, Temperature, SOC, 3DSIC, Test Schedule

S. K. Millican and K. K. Saluja, "Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 37-42.
96 ms
(Ver 3.3 (11022016))