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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 31-36
ABSTRACT
Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault testing. We show quantitatively using the SDQL metric that test quality is significantly reduced if the test patterns are generated with TSV stress-oblivious circuit models. We evaluate the impact on TSV stress on delay testing by considering layouts for several 3D logic-on-logic benchmarks. The test escape rate is higher for processes with lower yields. Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count. We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation.
INDEX TERMS
Through-silicon vias, Stress, Automatic test pattern generation, Delay, Integrated circuit modeling, TSV stress, 3D test, ATPG
CITATION

S. Deutsch, K. Chakrabarty, S. Panth and S. K. Lim, "TSV Stress-Aware ATPG for 3D Stacked ICs," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 31-36.
doi:10.1109/ATS.2012.61
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