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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 19-24
ABSTRACT
Introducing partial programmability in circuits by replacing some gates with look up tables (LUTs) can be an effective way to improve post-silicon or in-field rectification and debugging. Although finding configurations of LUTs that can correct the circuits can be formulated as a QBF problem, solving it by state-of-the-art QBF solvers is still a hard problem for large circuits and many LUTs. In this paper, we present a rectification and debugging method for combinational circuits with LUTs by repeatedly applying Boolean SAT solvers. Through the experimental results, we show our proposed method can quickly find LUT configurations for large circuits with many LUTs, which cannot be solved by a QBF solver.
INDEX TERMS
Table lookup, Debugging, Logic gates, Combinational circuits, Circuit faults, Field programmable gate arrays, Logic functions, satisfiability, rectification, debugging, look-up table
CITATION

S. Jo, T. Matsumoto and M. Fujita, "SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 19-24.
doi:10.1109/ATS.2012.55
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