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2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
ISSN: 1081-7735
ISBN: 978-1-4673-4555-2
pp: 13-18
Debugging of speed-limiting paths (speed paths) is a key challenge in development of Very-Large-Scale Integrated(VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to diagnose speed paths under timing variations. First timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on Boolean Satisfiability (SAT) diagnoses speed paths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites. In average, the diagnosis accuracy of 98:51% is achieved by our approach.
Logic gates, Circuit faults, Clocks, Debugging, Delay, Integrated circuit modeling, timing variation, automated debugging, failing speedpath

M. Dehbashi and G. Fey, "Automated Post-Silicon Debugging of Failing Speedpaths," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 13-18.
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