2012 IEEE 21st Asian Test Symposium (2012)
Niigata, Japan Japan
Nov. 19, 2012 to Nov. 22, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2012.39
Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed test application time, we take an approach to increase the number of the transfers tested concurrently. Evaluation results show that our approach is effective for that purpose.
Clocks, Synchronization, Testing, System-on-a-chip, Design for testability, Abstracts, cost-effective testing, scan testing, at-speed testing
H. Iwata, Y. Maeda, J. Matsushima and M. Takakura, "An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms," 2012 IEEE 21st Asian Test Symposium(ATS), Niigata, Japan Japan, 2012, pp. 1.