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2008 17th Asian Test Symposium (2008)
Nov. 24, 2008 to Nov. 27, 2008
ISSN: 1081-7735
ISBN: 978-0-7695-3396-4
pp: 377-382
Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.
Instruction checking, watchdog

R. Mariani, G. D. Natale and S. D. Carlo, "On-Line Instruction-Checking in Pipelined Microprocessors," 2008 17th Asian Test Symposium(ATS), vol. 00, no. , pp. 377-382, 2008.
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