The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2007)
Beijing, China
Oct. 8, 2007 to Oct. 11, 2007
ISSN: 1081-7735
ISBN: 0-7695-2890-2
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. xiii

Foreword (PDF)

pp. xiii
Introduction
Session 1A: Opening Session

Keynote Speech 1: New Paths for Test (PDF)

Jacob Abraham , University of Texas at Austin, USA
pp. 3

Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology (PDF)

Kary Chien , Semiconductor Manufacturing International (Shanghai) Corp.,China
pp. 9
Session 2A: Fault Modeling and Functional Test

The Region-Exhaustive Fault Model (Abstract)

Suriyaprakash Natarajan , Advanced Test Technology, Intel Corporation
Srinivas Patil , Advanced Test Technology, Intel Corporation
Abhijit Jas , Advanced Test Technology, Intel Corporation
pp. 13-18

Mining Sequential Constraints for Pseudo-Functional Testing (Abstract)

Michael S. Hsiao , Virginia Tech, Blacksburg, VA
Weixin Wu , Virginia Tech, Blacksburg, VA
pp. 19-24
Session 2B: Fault Diagnosis (I)

Fast Bridging Fault Diagnosis using Logic Information (Abstract)

A. Virazel , Universit? Montpellier II / CNRS, Cedex, France
A. Bosio , Universit? Montpellier II / CNRS, Cedex, France
P. Girard , Universit? Montpellier II / CNRS, Cedex, France
A. Rousset , Universit? Montpellier II / CNRS, Cedex, France
S. Pravossoudovitch , Universit? Montpellier II / CNRS, Cedex, France
C. Landrault , Universit? Montpellier II / CNRS, Cedex, France
pp. 33-38

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines (Abstract)

Hiroshi Takahashi , Ehime University
Takashi Aikyo , Ehime University
Yoshinobu Higami , Ehime University
Yuzo Takamatsu , Ehime University
Shuhei Kadoyama , Ehime University
pp. 39-44

Fault Dictionary Based Scan Chain Failure Diagnosis (Abstract)

Ruifeng Guo , Mentor Graphics Corp. Wilsonville, OR 97070 USA
Wu-Tung Cheng , Mentor Graphics Corp. Wilsonville, OR 97070 USA
Yu Huang , Mentor Graphics Corp. Wilsonville, OR 97070 USA
pp. 45-52
Session 2C: Panel Session

Test Education in the Global Economy (PDF)

Yinghua Min , Chinese Academy of Sciences, China
Jeremy Wang , Fabless Semiconductor Association, Asia Pacific
Jacob Abraham , Univ. of Texas, Austin, USA
Salvador Mir , TIMA, France
Cheng-Wen Wu , National TsingHua University, Taiwan
pp. 53
Session 3A: Delay Test (I)

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults (Abstract)

Shahdad Irajpour , University of Southern California, Los Angeles, CA
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
pp. 57-64

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults (Abstract)

Satoshi Ohtake , Nara Institute of Science and Technology
Yuki Yoshikawa , Hiroshima City University
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 65-68

Using Programmable On-Product Clock Generation (OPCG) for Delay Test (Abstract)

Brion Keller , Cadence Design Systems, Inc., Endicott, New York
Bibo Li , Cadence Design Systems, Inc., Endicott, New York
Tom Snethen , Cadence Design Systems, Inc., Endicott, New York
Anis Uzzaman , Cadence Design Systems, Inc., Endicott, New York
pp. 69-72

An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits (Abstract)

Elham K. Moghaddam , Sharif University of Technology, Tehran, IRAN
Shaahin Hessabi , Sharif University of Technology, Tehran, IRAN
pp. 73-78
Session 3B: Test Compression

A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding (Abstract)

Srimat T. Chakradhar , NEC Labs. America, Princeton, NJ 08540, USA
Wenlong Wei , NEC Labs. America, Princeton, NJ 08540, USA
Seongmoon Wang , NEC Labs. America, Princeton, NJ 08540, USA
pp. 79-86

Test Compression / Decompression Based on JPEG VLC Algorithm (Abstract)

Yusuke Nakashima , Hiroshima City University
Hideyuki Ichihara , Hiroshima City University
Tomoo Inoue , Hiroshima City University
Yukinori Setohara , Hiroshima City University
pp. 87-90

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos (Abstract)

Ahmad A. Al-Yamani , King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia
Mustafa Imran Ali , King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia
Aiman H. El-Maleh , King Fahd University of Petroleum & Minerals, Dhahran 31261, Saudi Arabia
pp. 91-94

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture (Abstract)

Katherine Shu-Min Li , NNational Sun Yat-Sen University, Taiwan
Sying-Jyan Wang , National Chung Hsing University, Taichung, Taiwan
Po-Chang Tsai , National Chung Hsing University, Taichung, Taiwan
Hung-Ming Weng , National Chung Hsing University, Taichung, Taiwan
pp. 95-100
Session 3C: Power Aware Test (I)

Resistive Bridging Faults DFT with Adaptive Power Management Awareness (Abstract)

Peter Harrod , ARM Limited, Cambridge UK
Bashir M. Al-Hashimi , University of Southampton, UK
S. Saqib Khursheed , University of Southampton, UK
Paul Rosinger , University of Southampton, UK
Urban Ingelsson , University of Southampton, UK
pp. 101-106

Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Dan Zhao , University at Louisiana at Lafayette, USA
Ronghua Huang , University at Louisiana at Lafayette, USA
pp. 107-110

An Efficient Peak Power Reduction Technique for Scan Testing (Abstract)

Meng-Fan Wu , National Taiwan University, Taipei 106, Taiwan
Jiun-Lang Huang , National Taiwan University, Taipei 106, Taiwan
Kai-Shun Hu , National Taiwan University, Taipei 106, Taiwan
pp. 111-114
Session 4A: DFT (I)

A RTL Testability Analyzer Based on Logical Virtual Prototyping (Abstract)

Greg Aldrich , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, OR 97070, USA
Nilanjan Mukherjee , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, OR 97070, USA
Yu Huang , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, OR 97070, USA
pp. 121-124

Optimum Test Set for Bridging Fault Detection in Reversible Circuits (Abstract)

Bhargab B. Bhattacharya , ACM Unit, Indian Statistical Institute, Kolkata
Dipak K. Kole Dipak K. Kole , University, Howrah 711 103, India
Debesh K. Das , University, Howrah 711 103, India
Hafizur Rahaman , University, Howrah 711 103, India
pp. 125-128

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis (Abstract)

Xin-Long Li , National Chung Hsing University, Taiwan
Katherine Shu-Min Li , National Sun Yat-Sen University, Taiwan
Sying-Jyan Wang , National Chung Hsing University, Taiwan
pp. 129-134
Session 4B: RF Test

A Test and Diagnosis Methodology for RF Transceivers (Abstract)

Chauchin Su , National Chiao Tung University, Hsinchu, 300, Taiwan
Hung-kai Chen , National Chiao Tung University, Hsinchu, 300, Taiwan
pp. 135-138

A BIST Technique for RF Voltage-Controlled Oscillators (Abstract)

Guo-Wei Huang , National Nano Device Laboratories, Hsinchu, R.O.C.
Yen-Chih Huang , National Taiwan University, Taipei, R.O.C.
Hsieh-Hung Hsieh , National Taiwan University, Taipei, R.O.C.
Liang-Hung Lu , National Taiwan University, Taipei, R.O.C.
pp. 143-148
Session 4C: Software Test

An Improved Test Case Generation Method of Pair-Wise Testing (Abstract)

Qian Feng-an , Tongji University, Shanghai 201804,China
Jiang Jian-hui , Tongji University, Shanghai 201804,China
pp. 149-154

System Testing using UML Models (Abstract)

Monalisa Sarma , Indian Institute of Technology Kharagpur, West Bengal - 721302, India
Rajib Mall , Indian Institute of Technology Kharagpur, West Bengal - 721302, India
pp. 155-158

Reconsideration of Software Reliability Measurements (Abstract)

Shiyi Xu , Shanghai University, Shanghai 200072, CHINA
pp. 159-164
Session 5A: Design Verification

An Accurate Analysis of Microprocessor Design Verification (Abstract)

Haihua Shen , Chinese Academy of Sciences, Beijing, China
Heng Zhang , Chinese Academy of Sciences, Beijing, China
pp. 165-171

Optimized Assignment Coverage Computation in Formal Verification of Digital Systems (Abstract)

Hamid Shojaei , Tehran University
Siamak Mohammadi , Tehran University
Majid Nabi , Tehran University
pp. 172-177

EHSAT Modeling from Algorithm Description for RTL Model Checking (Abstract)

Shujun Deng , Tsinghua University, Beijing, China
Jinian Bian , Tsinghua University, Beijing, China
Xiaoqing Yang , Tsinghua University, Beijing, China
Yanni Zhao , Tsinghua University, Beijing, China
pp. 178-186
Session 5B: SOC Test

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip (Abstract)

Krishnendu Chakrabarty , Duke University
Thomas Edison Yu , Nara Institute of Science and Technology, Japan
Hideo Fujiwara , Duke University
Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
pp. 187-192

Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC (Abstract)

Dooyoung Kim , Hanyang University, Korea
Juhee Han , Hanyang University, Korea
Sungju Park , Hanyang University, Korea
Jaehoon Song , Hanyang University, Korea
Hyunbean Yi , Hanyang University, Korea
pp. 193-198

Test Scheduling for Memory Cores with Built-In Self-Repair (Abstract)

Tomokazu Yoneda , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
Yuusuke Fukuda , Nara Institute of Science and Technology
pp. 199-206
Session 5C: Panel Session
Session 6A: Industry Session

IDDQ Test Challenges in Nanotechnologies: A Manufacturing Test Strategy (PDF)

Moo Kit Lee , Marvell Semiconductor
Peng Weng Ng , Marvell Semiconductor
Chin Hu Ong , Marvell Semiconductor
Yu Wei P?ng , Marvell Semiconductor
pp. 211

A Review of Power Strategies for DFT and ATPG (PDF)

Brion Keller , Cadence Design Systems, Inc., Endicott, New York 13850, USA
Tom Jackson , Cadence Design Systems, Inc., Endicott, New York 13850, USA
Anis Uzzaman , Cadence Design Systems, Inc., Endicott, New York 13850, USA
pp. 213

Concurrent Test Implementations (PDF)

Shawn Molavi , Broadcom Corporation, Irvine, CA
Toby McPheeters , Broadcom Corporation, Santa Clara, CA
pp. 214

Scan Diagnosis and Its Successful Industrial Applications (PDF)

Martin Keim , Mentor Graphics, 8005 SW Boeckman Road, Wilsonville, OR, USA
Wu Yang , Mentor Graphics, 8005 SW Boeckman Road, Wilsonville, OR, USA
Wu-Tung Cheng , Mentor Graphics, 8005 SW Boeckman Road, Wilsonville, OR, USA
Randy Klingenberg , Mentor Graphics, 8005 SW Boeckman Road, Wilsonville, OR, USA
Yu Huang , Mentor Graphics, 8005 SW Boeckman Road, Wilsonville, OR, USA
pp. 215
Session 6B: Analog Test

A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement (Abstract)

Ji-Jan Chen , Industrial Technology Research Institute, Hsinchu, Taiwan
Yu Lee , Industrial Technology Research Institute, Hsinchu, Taiwan
Nai-Chen Daniel Cheng , Industrial Technology Research Institute, Hsinchu, Taiwan
pp. 219-223

An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing (Abstract)

Dongwoo Hong , University of California, Santa Barbara, CA
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara, CA
pp. 224-229

Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods (Abstract)

Xinsong Zhang , University of Arkansas, Fayetteville
Simon S. Ang , University of Arkansas, Fayetteville
Chandra Carter , Texas Instruments Inc., Dallas, Texas, 75243 USA
pp. 230-238
Session 6C: Power Aware Test (II)

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits (Abstract)

L. Larguier , LIRMM, CNRS/University of Montpellier, 161 rue Ada - 34392 Montpellier Cedex 5 - France
M. Renovell , LIRMM, CNRS/University of Montpellier, 161 rue Ada - 34392 Montpellier Cedex 5 - France
F. Azais , LIRMM, CNRS/University of Montpellier, 161 rue Ada - 34392 Montpellier Cedex 5 - France
pp. 239-244

Effect of IR-Drop on Path Delay Testing Using Statistical Analysis (Abstract)

Yang Wu , University of Nebraska-Lincoln
Chunsheng Liu , University of Nebraska-Lincoln
Yu Huang , Mentor Graphics
pp. 245-250

Low Power Reduced Pin Count Test Methodology (Abstract)

Bing Li , Cadence Design Systems
Brian Foutz , Cadence Design Systems
Vivek Chickermane , Cadence Design Systems
Nitin Parimi , Cadence Design Systems
Krishna Chakravadhanula , Cadence Design Systems
pp. 251-258
Session 7A: Test Generation (I)

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects (Abstract)

Minjin Zhang , Chinese Academy of Sciences, Beijing, China
Xiaowei Li , Chinese Academy of Sciences, Beijing, China
pp. 259-264

Simulating Open-Via Defects (Abstract)

Piet Engelke , Albert-Ludwigs-University, Germany
Jie Jiang , Albert-Ludwigs-University, Germany
Stefan Spinner , Albert-Ludwigs-University, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 265-270

Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator (Abstract)

Yoshinobu Higami , Ehime University
Yuzo Takamatsu , Ehime University
Hiroshi Takahashi , Ehime University
Shin-ya Kobayashi , Ehime University
Kewal K. Saluja , Ehime University
pp. 271-274

Fault-dependent/independent Test Generation Methods for State Observable FSMs (Abstract)

Toshinori Hosokawa , Nihon University
Hideo Fujiwara , Nara Institute of Science and Technology
Ryoichi Inoue , Nihon University
pp. 275-280
Session 7B: Fault Diagnosis (II)

Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, USA
Wei Zou , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, USA
Huaxing Tang , Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, USA
Sudahkar M. Reddy , University of Iowa, Iowa City, Iowa
Chen Liu , University of Iowa
pp. 281-287

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability (Abstract)

Feijun Zheng , Zhejiang University
John Moondanos , Intel Corporation
Ziyad Hanna , Intel Corporation
Kwang-Ting Cheng , University of California at Santa Barbara
Xiaolang Yan , Zhejiang University, Hangzhou
pp. 288-294

Programmable Logic BIST for At-speed Test (Abstract)

Xijiang Lin , Mentor Graphics Corp.
Yu Huang , Mentor Graphics Corp.
pp. 295-300

Diagnostic Test Generation Targeting Equivalence Classes (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
pp. 301-306
Session 7C: Soft Error Issue

CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors (Abstract)

Shijian Zhang , Chinese Academy of Sciences, Beijing 100080, P.R.China
Weiwu Hu , Chinese Academy of Sciences, Beijing 100080, P.R.China
pp. 313-318

Monitoring Transient Errors in Sequential Circuits (Abstract)

Ramashis Das , University of Michigan
John P. Hayes , University of Michigan
pp. 319-322

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic (Abstract)

Shaohua Lei , Chinese Academy of Sciences, Beijing
Xiaowei Li , Chinese Academy of Sciences, Beijing
Yinhe Han , Chinese Academy of Sciences, Beijing
pp. 323-328
Session 8A: DFT (II)

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan (Abstract)

Gefu Xu , Auburn University, AL, USA
Adit D. Singh , Auburn University, AL, USA
pp. 335-340

An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing (Abstract)

Laung-Terng (L.-T.) WANG , SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, CA
Xiao-Xin FAN , Graduate School of Chinese Academy of Sciences, Beijing
Yu HU , Chinese Academy of Sciences
pp. 341-348
Session 8B: Memory Test (I)

A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories (Abstract)

Li-Ming Denq , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 349-354

CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs (Abstract)

Hsiang-Huang Wu , Realtek Semiconductor Corp., Hsinchu, Taiwan
Chi-Feng Wu , Realtek Semiconductor Corp., Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
Jin-Fu Li , National Central University, Jhongli, Taiwan
pp. 355-360
Session 8C: Panel Session

Test Roles in Diagnosis and Silicon Debug (PDF)

Takashi Aikyo , Fujitsu/STARC, Japan
Tom Jackson , Cadence Design Systems, U.S.A.
Anis Uzzaman , Cadence Design Systems, U.S.A.
Robert Aitken , ARM, U.S.A.
Takeshi Onodera , Sony, Japan
Rajesh Galivanche , Intel, U.S.A.
Fidel Muradali , National Semiconductor, U.S.A.
pp. 367
Session 9A: BIST

Programmable Scan-Based Logic Built-In Self Test (Abstract)

Thomas Rinderknecht , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
Liyang Lai , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, OR 97070, USA
pp. 371-377

Evaluation of a BIST Technique for CMOS Imagers (Abstract)

G. Sicard , TIMA Laboratory, Grenoble, FRANCE
L. Lizarraga , TIMA Laboratory, Grenoble, FRANCE
S. Mir , TIMA Laboratory, Grenoble, FRANCE
pp. 378-383

Built-In Speed Grading with a Process-Tolerant ADPLL (Abstract)

Shi-Yu Huang , National Tsing-Hua University, Taiwan
Hsuan-Jung Hsu , National Tsing-Hua University, Taiwan
Chun-Chieh Tu , National Tsing-Hua University, Taiwan
pp. 384-392
Session 9B: Current Test

Testing RF Components with Supply Current Signatures (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Shreyas Sen , Georgia Institute of Technology, Atlanta, GA
S. Sermet Akbay , Georgia Institute of Technology, Atlanta, GA
pp. 393-398

Current Testable Design of Resistor String DACs (Abstract)

Yutaka Hata , University of Tokushima
Tomomi Nishida , University of Tokushima
Yukiya Miura , Tokyo Metropolitan University
Masaki Hashizume , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
pp. 399-403

Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC (Abstract)

Yang Zhong , RWTH-Aachen University, Aachen, Germany
Henk van de Donk , Design Methods and Solutions, NXP Semiconductors, Eindhoven, the Netherlands
Liquan Fang , Automotive Business Line, NXP Semiconductors, 6534 AE Nijmegen, the Netherlands
pp. 404-412
Session 9C: Power Aware Test (III)

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs (Abstract)

Nan-Cheng Lai , National Chung-Hsing University, Taiwan
Sying-Jyan Wang , National Chung-Hsing University, Taiwan
pp. 413-418

Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering (Abstract)

Santanu Chattopadhyay , E & ECE, IIT Kharagpur, India
Pradeep Kumar Choudhary , E & ECE, IIT Kharagpur, India
Chandan Giri , E & ECE, IIT Kharagpur, India
pp. 419-424

Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique (Abstract)

Wei-Chung Kao , National Taiwan University
Bing-Chuan Bai , National Taiwan University
Bo-Hua Chen , National Taiwan University
Shyue-Tsong Shen , National Taiwan University
James C.-M. Li , National Taiwan University
pp. 425-432
Session 10A: Test Generation (II)

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges (Abstract)

Piet Engelke , Albert-Ludwigs-University
Michel Renovell , LIRMM - UMII, Montpellier, France
Ilia Polian , Albert-Ludwigs-University
Bettina Braitling , Albert-Ludwigs-University
pp. 433-438

Symbolic Path Sensitization Analysis and Applications (Abstract)

Shashank K. Mehta , Indian Institute of Technology, India
Sharad C. Seth , University of Nebraska - Lincoln
Jian Kang , University of Nebraska - Lincoln
pp. 439-444

Improving Test Pattern Compactness in SAT-based ATPG (Abstract)

Stephan Eggersgluess , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 445-452
Session 10B: NOC/SOC Test

An HDL-Based Platform for High Level NoC Switch Testing (Abstract)

Elnaz Koopahi , University of Tehran, Tehran, Iran
Zainalabedin Navabi , University of Tehran, Tehran, Iran
Armin Alaghi , University of Tehran, Tehran, Iran
Mahshid Sedghi , University of Tehran, Tehran, Iran
pp. 453-458

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing (Abstract)

Tomokazu Yoneda , Nara Institute of Science and Technology
Fawnizu Azmadi Hussin , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 459-462

Test Efficiency Analysis and Improvement of SOC Test Platforms (Abstract)

Tong-Yu Hsieh , National Cheng Kung University
Jian-Jhih You , National Cheng Kung University
Kuen-Jong Lee , National Cheng Kung University
pp. 463-466

Block Marking and Updating Coding in Test Data Compression for SoC (Abstract)

Huaguo Liang , Hefei University of Technology, 230009 Hefei, China
Cuiyun Jiang , Hefei University of Technology, 230009 Hefei, China
Wenfa Zhan , Hefei University of Technology, 230009 Hefei, China
Lei Zhang , Hefei University of Technology, 230009 Hefei, China
pp. 467-472
Session 10C: Analog Production Test #1

How the noise floor affects the production yield (PDF)

Akinori Maeda , Verigy Japan K.K. Hachioji Tokyo Japan
pp. 474

Integrated Test Solution for embedded UHF/RF SOC (PDF)

Sean Lu , Broadcom Corporation, Irvine, CA
Dee-Won Lee , Verigy Ltd., Irvine, CA
pp. 475
Session 11A: Delay Test (II)

On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis (Abstract)

Sandeep K. Gupta , University of Southern California
I-De Huang , University of Southern California
pp. 485-492

Test Generation for Timing-Critical Transition Faults (Abstract)

Janusz Rajski , Mentor Graphics Corp.
Mark Kassab , Mentor Graphics Corp.
Xijiang Lin , Mentor Graphics Corp.
pp. 493-500
Session 11B: Memory Test (II)

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior (Abstract)

A. Virazel , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier - UM2/CNRS, France
A. Ney , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier - UM2/CNRS, France
P. Girard , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier ? UM2/CNRS, France
C. Landrault , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier - UM2/CNRS, France
M. Bastian , Infineon Technologies France
V. Gouin , Infineon Technologies France
S. Pravossoudovitch , Laboratoire d?Informatique, de Robotique et de Micro?lectronique de Montpellier - UM2/CNRS, France
pp. 507-510
Session 11C: Analog Production Test #2

Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC (PDF)

Deng Yue , Verigy Shanghai Application Development Center
pp. 518

Top 5 Issues in Practical Testing of High-Speed Interface Devices (PDF)

Takahiro J. Yamaguchi , Advantest Laboratories, Ltd., Sendai, Miyagi, Japan
pp. 519
Special Sessions on Analog Production Test

Special Session: Analog Production Test (PDF)

Fidel Muradali , National Semiconductor
Jochen Rivoir , Verigy
pp. 523
Author Index

Author Index (PDF)

pp. 525
Call for Papers ATS 2008
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