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2012 IEEE 21st Asian Test Symposium (2006)
Fukuoka, Japan
Nov. 20, 2006 to Nov. 23, 2006
ISSN: 1081-7735
ISBN: 0-7695-2628-4
TABLE OF CONTENTS

Foreword (PDF)

pp. xi

list-reviewer (PDF)

pp. xvi
Introduction

Foreword (PDF)

pp. xi

Reviewers (PDF)

pp. xvi

Tutorial 2 (PDF)

pp. xx
Session 2A: Test Power Reduction

Power-Aware Test Data Compression for Embedded IP Cores (Abstract)

N. Badereddine , Universit? de Montpellier II / CNRS, Cedex, France
C. Landrault , Duke University
K. Chakrabarty , Duke University
Z. Wang , Duke University
S. Pravossoudovitch , Duke University
P. Girard , Universit? de Montpellier II / CNRS, Cedex, France
pp. 5-10

A Scan Chain Adjustment Technology for Test Power Reduction (Abstract)

Xiaowei LI , Advanced Test Technology Laboratory, Institute of Computing Technology, Beijing, China
Jia LI , University of Chinese Academy of Sciences, Beijing
Yu HU , Advanced Test Technology Laboratory, Institute of Computing Technology, Beijing, China
pp. 11-16

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure (Abstract)

Youbean Kim , Yonsei University
Sungho Kang , Yonsei University
Incheol Kim , Yonsei University
Dongsup Song , Yonsei University
Kicheol Kim , Yonsei University
pp. 17-24
Session 2B: Memory Test

An Enhanced SRAM BISR Design with Reduced Timing Penalty (Abstract)

Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
Li-Ming Denq , National Tsing Hua University, Hsinchu, Taiwan
Tzu-Chiang Wang , National Tsing Hua University, Hsinchu, Taiwan
pp. 25-30

Memory Fault Simulator for Static-Linked Faults (Abstract)

S. Di Carlo , Politecnico di Torino, Italy
A. Bosio , Politecnico di Torino, Italy
P. Prinetto , Politecnico di Torino, Italy
A. Benso , Politecnico di Torino, Italy
G. Di Natale , Politecnico di Torino, Italy
pp. 31-36

Test/Repair Area Overhead Reduction for Small Embedded SRAMs (Abstract)

Qiang Xu , Chinese University of Hong Kong, Shatin, N.T., Hong Kong
Baosheng Wang , ATI Technologies Inc., 1 Commerce Valley Drive East, Markham, ON, Canada
pp. 37-44
Session 2C: Test Techniques

Histogram Based Testing Strategy for ADC (Abstract)

Soon-Jyh Chang , National Cheng-Kung University, Tainan, Taiwan
Bin-Da Liu , National Cheng-Kung University, Tainan, Taiwan
Hsin-Wen Ting , National Cheng-Kung University, Tainan, Taiwan
pp. 51-54
Session 3A: IDDQ and Burn-in Test

Delta-IDDQ Testing of Resistive Short Defects (Abstract)

Bernd Becker , Albert-Ludwigs-University, Germany
Piet Engelke , Albert-Ludwigs-University, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
Michel Renovell , LIRMM - UMII, France
Hans Manhaeve , Q-Star Test, Belgium
pp. 63-68

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests (Abstract)

Yukiya Miura , Tokyo Metropolitan University
Masaki Hashizume , Univ.of Tokushima, Japan
Masato Nakanishi , Univ.of Tokushima, Japan
Hiroyuki Yotsuyanagi , Univ.of Tokushima, Japan
pp. 69-74

ATPG for Dynamic Burn-In Test in Full-Scan Circuits (Abstract)

Stefano DI CARLO , Politecnico di Torino, Italy
Alfredo BENSO , Politecnico di Torino, Italy
Giorgio DI NATALE , Politecnico di Torino, Italy
Paolo PRINETTO , Politecnico di Torino, Italy
Alberto BOSIO , Politecnico di Torino, Italy
pp. 75-82
Session 3B: High-Level Test

Spectral RTL Test Generation for Gate-Level Stuck-at Faults (Abstract)

Vishwani D. Agrawal , Auburn University
Nitin Yogi , Auburn University
pp. 83-88

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains (Abstract)

Ling-yi Liu , Chinese Academy of Sciences, Beijing, China
Tao Lv , Chinese Academy of Sciences, Beijing, China
Hua-wei Li , Chinese Academy of Sciences, Beijing, China
Yang Zhao , Chinese Academy of Sciences, Beijing, China
Xiao-wei Li , Chinese Academy of Sciences, Beijing, China
pp. 89-94
Session 3C: Design Verification

The Potential and Limitation of Probability-Based Combinational Equivalence Checking (Abstract)

Chun-Yao Wang , National Tsing Hua University, HsinChu, Taiwan R.O.C.
Shih-Chieh Wu , National Tsing Hua University, HsinChu, Taiwan R.O.C.
Jan-An Hsieh , National Tsing Hua University, HsinChu, Taiwan R.O.C.
pp. 103-108

Verification Methodology for Self-Repairable Memory Systems (Abstract)

Jin-Fu Li , National Central University Jhongli, Taiwan
Chun-Hsien Wu , National Central University Jhongli, Taiwan
pp. 109-114

A Soft Error Tolerant LUT Cascade Emulator (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Iizuka 820-8502, Japan
Hiroki Nakahara , Kyushu Institute of Technology, Iizuka 820-8502, Japan
pp. 115-124
Session 4A: Special Session
Industry (Short Presentation)

How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 Minutes (PDF)

Jing Jiang , Rambus Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
Paul Wong , Rambus Inc., 4440 El Camino Real, Los Altos, CA 94022, USA
pp. 126

iDEN Phone System Test: An Automation Approach (PDF)

Ong Kein Wei , iDEN Subscriber Test Group Global Software Group Motorola, Penang
Muhammad Aiman Mazlan , iDEN Subscriber Test Group Global Software Group Motorola, Penang
Cindy Phang Sim Sim , iDEN Subscriber Test Group Global Software Group Motorola, Penang
pp. 128

Development of practical ATPG tool with flexible interface (PDF)

Masayoshi YOSHIMURA , FLEETS Sawara-ku, Fukuoka, 814-0001, Japan
Yusuke MATSUNAGA , Kyushu University
pp. 129

Mentor Graphics DFT to Navigate Nanometer Test Challenges (PDF)

Ron Press , Mentor Graphics Corp., USA
Tatsuo Sakajiri , Mentor Graphics Japan Co. Ltd., Japan
Takeo Kobayashi , Mentor Graphics Corp., USA
Greg Aldrich , Mentor Graphics Corp., USA
pp. 130

The Application of BIST-Aided Scan Test for Real Chips (PDF)

Michiaki Emori , FUJITSU LIMITED
Takahisa Hiraide , FUJITSU LIMITED
Hideaki Konishi , FUJITSU LIMITED
pp. 131

A Scalable Architecture for On-Chip Compression: Options and Trade-Offs (PDF)

Brion Keller , Cadence Design Systems, Inc, Endicott, New York, USA
Vivek Chickermane , Cadence Design Systems, Inc, Endicott, New York, USA
Anis Uzzaman , Cadence Design Systems, Inc, Endicott, New York, USA
pp. 132
Session 5A: Panel Session

Practical Needs and Wants for Silicon Debug and Diagnosis (PDF)

Fidel Muradali , National Semiconductor Corporation
pp. 135
Session 6A: Delay Test

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects (Abstract)

Yasuo Sato , Semiconductor Technology Academic Research Center, Yokohama, Japan
Takashi Aikyo , Semiconductor Technology Academic Research Center, Yokohama, Japan
Randy Klingenberg , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Shuji Hamada , Semiconductor Technology Academic Research Center, Yokohama, Japan
Chen Wang , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Takeo Kobayashi , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Xijiang Lin , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 139-146

Not all Delay Tests Are the Same - SDQL Model Shows True-Time (Abstract)

Mick Tegethoff , Cadence Design Systems, Inc. Endicott, New York, USA
Bibo Li , Cadence Design Systems, Inc. Endicott, New York, USA
Kevin Mc Cauley , Cadence Design Systems, Inc. Endicott, New York, USA
Anis Uzzaman , Cadence Design Systems, Inc. Endicott, New York, USA
Shuji Hamada , Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan
Yasuo Sato , Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan
pp. 147-152

At-Speed Testing with Timing Exceptions and Constraints-Case Studies (Abstract)

Toshiharu Asaka , Semiconductor Technology Academic Research Center, Yokohama, Japan
Dhiraj Goswami , Mentor Graphics Corporation, Wilsonville, OR 97070
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR 97070
Takashi Aikyo , Semiconductor Technology Academic Research Center, Yokohama, Japan
Bruce Swanson , Mentor Graphics Corporation, Wilsonville, OR 97070
Mark Kassab , Mentor Graphics Corporation, Wilsonville, OR 97070
Yasuo Sato , Semiconductor Technology Academic Research Center, Yokohama, Japan
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070
Takeo Kobayashi , Mentor Graphics Corporation, Wilsonville, OR 97070
Darryl Walters , Mentor Graphics Corporation, Wilsonville, OR 97070
pp. 153-162
Session 6B: Scan Test Techniques (1)

A New Scan Design Technique Based on Pre-Synthesis Thru Functions (Abstract)

Chia Yee Ooi , Nara Institute of Science and Technology Kansai Science City
Hideo Fujiwara , Nara Institute of Science and Technology Kansai Science City
pp. 163-168

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage (Abstract)

Kuo-Lin Peng , National Chung Hsing University, Taichung, Taiwan
Katherine Shu-Min Li , National Chung Hsing University, Taichung, Taiwan
Sying-Jyan Wang , National Chung Hsing University, Taichung, Taiwan
pp. 169-174
Session 6C: Reliable Circuit Design

Study of N-Detectability in QCA Designs (Abstract)

Biplab K Sikdar , Bengal Engineering and Science University, India
pp. 183-188

A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure (Abstract)

Shiwei Ma , Shanghai University, Shanghai 200072 China
Ming Li , Shanghai University, Shanghai 200072 China
Jialin Cao , Shanghai University, Shanghai 200072 China
Feng Ran , Shanghai University, Shanghai 200072 China
Shiyi Xu , Shanghai University, Shanghai 200072 China
pp. 189-194

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs (Abstract)

Naghmeh Karimi , University of Tehran, 14399 Tehran, IRAN
Shahrzad Mirkhani , University of Tehran, 14399 Tehran, IRAN
Zainalabedin Navabi , University of Tehran, 14399 Tehran, IRAN
pp. 195-202
Session 7A: Defect Diagnosis

Interconnect Open Defect Diagnosis with Physical Information (Abstract)

Wei Zou , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, U.S.A
Wu-Tung Cheng , Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070, U.S.A
Sudhakar M. Reddy , University of Iowa Iowa City, IA 52242, U.S.A
pp. 203-209

Defect Diagnosis - Reasoning Methodology (Abstract)

Yasuo Sato , Semiconductor Technology Academi c Research Center, Yokohama, Japan
Kenji Norimatsu , Semiconductor Technology Academi c Research Center, Yokohama, Japan
Kazushi Sugiura , Semiconductor Technology Academi c Research Center, Yokohama, Japan
Masaru Sanada , Kochi University of Technology, Kochi, Japan
Yutaka Yoshizawa , Semiconductor Technology Academi c Research Center, Yokohama, Japan
Reisuke Shimoda , Semiconductor Technology Academi c Research Center, Yokohama, Japan
pp. 209-214

Diagnosis of delay faults due to resistive bridges, delay variations and defects (Abstract)

Sandeep K. Gupta , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
Lei Wang , University of Southern California, Los Angeles, CA
pp. 215-224
Session 7B: Scan Test Techniques (2)

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction (Abstract)

Sying-Jyan Wang , National Chung-Hsing University, Taiwan, ROC
Po-Chang Tsai , National Chung-Hsing University, Taiwan, ROC
pp. 225-230

Test Data Compression Based on Clustered Random Access Scan (Abstract)

Yin-He Han , Chinese Academy of Sciences
Yu Hu , Chinese Academy of Sciences
Wei Wang , Chinese Academy of Sciences
Xiao-Qing Wen , Kyushu Institute of Technology, Japan
Xiao-Wei Li , Chinese Academy of Sciences
Laung-Terng(L.T) Wang , SynTest Technologies, Inc., Sunnyvale 94086, U.S.A.
Hua-Wei Li , Chinese Academy of Sciences
Jia Li , Chinese Academy of Sciences
Cheng Li , Chinese Academy of Sciences
pp. 231-236

Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition (Abstract)

Jinkyu Lee , University of Texas, Austin, TX
Nur A. Touba , University of Texas, Austin, TX
pp. 237-244
Session 7C: Analog DFT

A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters (Abstract)

Jiseon Park , University of Texas at Austin
Jacob A. Abraham , University of Texas at Austin
Hongjoong Shin , University of Texas at Austin
pp. 245-250

A Digital BIST Methodology for Spread Spectrum Clock Generators (Abstract)

Jenchien Hsu , National Chiao Tung University, Hsinchu 300, Taiwan
Maohsuan Chou , National Chiao Tung University, Hsinchu 300, Taiwan
Chauchin Su , National Chiao Tung University, Hsinchu 300, Taiwan
pp. 251-254

A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems (Abstract)

Hao-Chiao Hong , National Chiao Tung University
Sheng-Chuan Liang , National Chiao Tung University
pp. 255-264
Session 8A: Defect ATPG

Test Generation for Weak Resistive Bridges (Abstract)

Shahdad Irajpour , University of Southern California, Los Angeles, CA
Melvin A. Breuer , University of Southern California, Los Angeles, CA
Sandeep K. Gupta , University of Southern California, Los Angeles, CA
pp. 265-272

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency (Abstract)

B. Becker , Albert-Ludwigs University, Germany
M. Comte , LIRMM-UMR C5506 CNRS
M. Renovell , LIRMM-UMR C5506 CNRS
P. Engelke , Albert-Ludwigs University, Germany
I. Polian , Albert-Ludwigs University, Germany
pp. 273-278

An Effective Test Pattern Generation for Testing Signal Integrity (Abstract)

Youngkyu Park , Yonsei Univeristy
DaeYeal Lee , Yonsei Univeristy
Myung-Hoon Yang , Yonsei Univeristy
Yongjoon Kim , Yonsei Univeristy
Sungho Kang , Yonsei Univeristy
pp. 279-286
Session 8B: Reconfigurabilities in BIST

A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR
Sudhakar Reddy , University of Iowa, Iowa City, IA
Nilanjan Mukherjee , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR
Xiaogang Du , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR
Chris Hill , Mentor Graphics Corporation, 8005 S.W. Boeckman Rd., Wilsonville, OR
pp. 287-292

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing (Abstract)

Zainalabedin Navabi , University of Tehran, Iran
Mahnaz Sadoughi Yarandi , University of Tehran, Iran
Armin Alaghi , University of Tehran, Iran
pp. 293-298

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture (Abstract)

Dong Xiang , Tsinghua University
Jiaguang Sun , Tsinghua University
Khrismendu Chakrabarty , Duke University
Yang Zhao , Tsinghua University
pp. 299-306
Session 8C: Solutions for Jitter Problems

Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock Jitter (Abstract)

Shalabh Goya , Georgia Institute of Technology
Yanan Shieh , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 307-312

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range (Abstract)

Chung-Yi Li , National Tsing Hua University
Chia-Yuan Chou , National Tsing Hua University
Tsin-Yuan Chang , National Tsing Hua University
pp. 313-317

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter (Abstract)

Jiun-Lang Huang , National Taiwan University, Taipei 106, Taiwan
pp. 318-326
Session 9A: Test Compression (1)

Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing (Abstract)

Hidehiko Kita , Graduate School of Engineering, Mie University
Haruhiko Takase , Graduate School of Engineering, Mie University
Tsuyoshi Shinogi , Graduate School of Engineering, Mie University
Naotsugu Ikeda , Graduate School of Engineering, Mie University
Terumine Hayashi , Graduate School of Engineering, Mie University
pp. 327-332

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs (Abstract)

Michael L. Bushnell , Rutgers University
Seongmoon Wang , NEC Laboratories America, Princeton, NJ
Rajamani Sethuram , Rutgers University
Srimat T. Chakradhar , NEC Laboratories America, Princeton, NJ
pp. 339-348
Session 9B: Diagnosis Algorithms

Fanout-based fault diagnosis for open faults on pass/fail information (Abstract)

Yuzo Takamatsu , Ehime University, JAPAN
Koji Yamazaki , Meiji University, JAPAN
pp. 349-353

Diagnosis of Transistor Shorts in Logic Test Environment (Abstract)

Yuzo Takamatsu , Ehime University
Yoshinobu Higami , Ehime University
Kewal K. Saluja , University of Wisconsin - Madison
Sin-ya Kobayashi , Ehime University
Hiroshi Takahashi , Ehime University
pp. 354-359

The Next Step in Volume Scan Diagnosis: Standard Fail Data Format (Abstract)

Ajay Khoche , Verigy, Santa Clara CA, USA
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR
Wu Yang , Mentor Graphics Corporation, Wilsonville, OR
Andreas Leininger , Infineon Technologies AG Am Campeon 1-12 Munich, Germany
Martin Fischer , Verigy, Boeblingen, Germany
Randy Klingenberg , Mentor Graphics Corporation, Wilsonville, OR
Nagesh Tamarapalli , Mentor Graphics Corporation, Wilsonville, OR
pp. 360-368
Session 9C: DFT for Processors and ASICs

DFT of the Cell Processor and its Impact on EDA Test Softwar (Abstract)

Louis Bushard , IBM Corp., Rochester MN
Brion Keller , Cadence Design Systems Inc., Endicott, NY
Steven Ferguson , IBM Corp., Austin, TX
Nathan Chelstrom , Intrinsity, Austin, TX
pp. 369-374

Design for Testability of Software-Based Self-Test for Processors (Abstract)

Masato Nakazato , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
Michiko Inoue , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 375-380

Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology (Abstract)

Brian Foutz , Cadence Design Systems
Vivek Chickermane , Cadence Design Systems
Gary Kunselman , IBM Corp.
Harry Linzer , IBM Corp.
Bing Li , Cadence Design Systems
pp. 381-388
Session 10A: Test Compression (2)

BCH-based Compactors of Test Responses with Controllable Masks (Abstract)

Samiha Mourad , Santa Clara University
Xiaoshu Qian , Intel Corporation
Taweesak Reungpeerakul , Santa Clara University
pp. 395-401

Expansion of Convolutional Compactors over Galois Field (Abstract)

Satoshi Fukumoto , Tokyo Metropolitan University, Tokyo, Japan
Kazuhiko Iwasaki , Tokyo Metropolitan University, Tokyo, Japan
Masayuki Arai , Tokyo Metropolitan University, Tokyo, Japan
pp. 401-408
Session 10B: Diagnosis Techniques

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester (Abstract)

Yoshiyuki Nakamura , NEC Electronics Corporation, Kawasaki, Japan
Hideo Fujiwara , Nara Institute of Science and Technology
Kewal K. Saluja , University of Wisconsin-Madison, WI 53706-1691, USA
Thomas Clouqueur , Nara Institute of Science and Technology
pp. 409-414

Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis (Abstract)

Sanae Seike , IBM Industrial Solution Co., Ltd., Tokyo, Japan
Satoshi Tanaka , Renesas Technology Corporation, Tokyo, Japan
Vivek Chickermane , Cadence Design Systems, New York, USA
Ken Namura , IBM Industrial Solution Co., Ltd., Tokyo, Japan
Azumi Kobayashi , Renesas Technology Corporation, Tokyo, Japan
Hiroyuki Adachi , Renesas Technology Corporation, Tokyo, Japan
Dale Meehl , Cadence Design Systems, New York, USA
Anis Uzzaman , Cadence Design Systems, New York, USA
Shinichi Arima , Cadence Design Systems, New York, USA
Yukio Ohya , IBM Industrial Solution Co., Ltd., Tokyo, Japan
pp. 415-420

Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor (Abstract)

Sverre Wichlund , Nordic Semiconductor ASA
Einar J. Aas , Norwegian University of Science and Technology
pp. 421-430
Session 10C: Network Issues

An External Test Approach for Network-on-a-Chip Switches (Abstract)

Vineeth Govind , Tallinn University of Technology
Jaan Raik , Tallinn University of Technology
Raimund Ubar , Tallinn University of Technology
pp. 437-442

Plug once, test everything (Abstract)

Ariel Sabiguero Yawelak , Universidad de la Republica Montevideo, Uruguay
Cesar Viho , Institut de Recherche en Informatique et Systemes Aleatoires Campus de Beaulieu, Rennes, France
pp. 443-448
Author Index

Author Index (PDF)

pp. 449
Call for Papers ATS 2007
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