The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2005)
Calcutta, India
Dec. 18, 2005 to Dec. 21, 2005
ISSN: 1081-7735
ISBN: 0-7695-2481-8
TABLE OF CONTENTS
Introduction

list-reviewer (PDF)

pp. xxii

Foreword (PDF)

pp. xv

TTTC Introduction (PDF)

pp. xxiv

TTEP Introduction (PDF)

pp. xxvii
Cover
Introduction

Foreword (PDF)

pp. xv
Tutorials

T1: Design for Manufacturability (PDF)

Yervant Zorian , Virage Logic, USA
Juan-Antonio Carballo , IBM Corporation, USA
pp. xxviii-xxix
Plenary Talk

Design for Testability: The Path to Deep Submicron (PDF)

Thomas W. Williams , Synopsys Fellow, Synopsys, USA
pp. xxxi
Banquet Speeches

DFT Aware Layout - Layout Aware DFT (PDF)

Sanjiv Taneja , Cadence Design Systems, USA
pp. xxxii
Invited Talks

Faults and Tests in Quantum Circuits (PDF)

John P. Hayes , University of Michigan, Ann Arbor, USA
pp. xxxiv
Session A1: Analog and RF Testing: I

Robust Built-In Test of RF ICs Using Envelope Detectors (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, Atlanta, GA
Donghoon Han , Georgia Institute of Technology, Atlanta, GA
pp. 2-7

Delay Defect Characterization Using Low Voltage Test (Abstract)

Gefu Xu , ECE Auburn University Auburn, AL.
Adit D. Singh , ECE Auburn University Auburn, AL.
Haihua Yan , Synopsys Inc., Mountain View, CA., USA
pp. 8-13

Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester (Abstract)

Shalabh Goyal , Georgia Institute of Technology,USA
Michael Purtell , National Semiconductor Corporation,USA
pp. 14-17

IDDQ Testing Method using a Scan Pattern for Production Testing (Abstract)

Yoshiyuki GOI , Matsushita Electric Industrial Co., Ltd.
Junichi HIRASE , Matsushita Electric Industrial Co., Ltd.
Yoshiyuki TANAKA , Matsushita Electric Industrial Co., Ltd.
pp. 18-21

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips (Abstract)

Lei Wu , University of Bremen, ITEM, Otto-Hahn-Allee-NW1, Bremen, Germany.
Juergen Schloeffel , Philips Semiconductors GmbH, DTC, George-Heyken-Strasse 1, Germany.
Walter Anheier , University of Bremen, ITEM, Otto-Hahn-Allee-NW1, Germany.
Ajoy K. Palit , University of Bremen, ITEM, Otto-Hahn-Allee-NW1, Bremen, Germany.
Kishore K. Duganapalli , University of Bremen, ITEM, Otto-Hahn-Allee-NW1, Germany.
pp. 22-27
Session B1: Verification, On-line and Software Testing

An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications (Abstract)

Nikolaos D. Liveris , Northwestern University, Evanston, IL
Hai Zhou , Northwestern University, Evanston, IL
Prithviraj Banerjee , University of Illinois, Chicago, IL
pp. 28-33

Block-based Schema-driven Assertion Generation for Functional Verification (Abstract)

Amir Hekmatpour , IBM System & Technology Group, Research Triangle Park, NC
Azadeh Salehi , IBM Software Group, Lotus, Westford, MA USA
pp. 34-39

A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores (Abstract)

M Prasanth , Indian Institute of Technology Madras Chennai, India
Kailasnath Maneparambil , Intel Corporation, Chandler, AZ, USA
K Uday Bhaskar , Indian Institute of Technology Madras Chennai, India
V Kamakoti , Indian Institute of Technology Madras Chennai, India
pp. 40-45

The Automatic Generation of Basis Set of Path for Path Testing (Abstract)

Li Xiaowei , Technology, Chinese Academy of Science
Zhang Guangmei , Academy of Sciences Shan Dong Agriculture University
Chen Rui , Chinese Academy of Sciences
Han Congying , Shan Dong University of Science and Technology
pp. 46-51
Session A2: Analog and RF Testing: II

Optimal Schemes for ADC BIST Based on Histogram (Abstract)

Yong-sheng WANG , Harbin Institute of Technology, Harbin, China
Yi-zheng YE , Harbin Institute of Technology, Harbin, China
Feng-chang LAI , Harbin Institute of Technology, Harbin, China
Jin-xiang WANG , Harbin Institute of Technology, Harbin, China
pp. 52-57

A 5 Gbps Wafer-Level Tester (Abstract)

A. M. Majid , Georgia Institute of Technology, USA
J. V. Karia , Georgia Institute of Technology, USA
D.C. Keezer , Georgia Institute of Technology, USA
pp. 58-63

Low-cost Production Test of BER for Wireless Receivers (Abstract)

Achintya Halder , Georgia Institute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 64-69

Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test (Abstract)

Shaolei Quan , Michigan State University, US
Qiang Qiang , Synopsys, Inc.
Chin-Long Wey , Natinal Central University, Taiwan
pp. 70-75
Session B2: Self-Checking, On-line and Software Testing

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors (Abstract)

M. Gossel , University of Potsdam, Germany
V. Ocheretnij , University of Potsdam, Germany
E. S. Sogomonyan , University of Potsdam, Germany
D. Marienfeld , University of Potsdam, Germany
pp. 76-81

A State Machine for Detecting C/C++ Memory Faults (Abstract)

Guangyan Huang , Institute of Computing Technology, China
Guangmei Zhang , Shan Dong Agriculture University, China
Yunzhan Gong , Academy of Armored Forces Engineering, China
Xiaowei Li , Institute of Computing Technology, China
pp. 82-87

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models (Abstract)

A Patra , Advanced VLSI Design Laboratory, IIT Kharagpur
S Mukhopadhyay , Advanced VLSI Design Laboratory, IIT Kharagpur
S Biswas , Advanced VLSI Design Laboratory, IIT Kharagpur
R Jha , Advanced VLSI Design Laboratory, IIT Kharagpur
P Srikanth , Advanced VLSI Design Laboratory, IIT Kharagpur
D Sarkar , Advanced VLSI Design Laboratory, IIT Kharagpur
pp. 88-93

Boundary Value Testing based on UML Models (Abstract)

Rajib Mall , Indian Institute of Technology, Kharagpur, India
Philip Samuel , Indian Institute of Technology, Kharagpur, India
pp. 94-99
Session A3: Interconnect Testing

Random Jitter Testing Using Low Tap-Count Delay Lines (Abstract)

Jiun-Lang Huang , National Taiwan University, Taipei, Taiwan
pp. 100-105

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle (Abstract)

Wen-Ching Wu , Industrical Technology Research Institute, Taiwan
Ming-Shae Wu , National Chiao Tung University, Taiwan
Chung-Len Lee , National Chiao Tung University, Taiwan
Yeong-Jar Chang , Industrical Technology Research Institute, Taiwan
pp. 106-111

A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects (Abstract)

Wichian Sirisaengtaksin , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 112-119

Non-robust Test Generation for Crosstalk-Induced Delay Faults (Abstract)

Xiao-Wei Li , Chinese Academy of Sciences, Beijing
Yong-Jun Xu , Chinese Academy of Sciences, Beijing
Hua-Wei Li , Chinese Academy of Sciences, Beijing
Pei-Fu Shen , Beijing Normal University, Beijing
pp. 120-125
Session B3: BIST

Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST (Abstract)

Dong Xiang , Tsinghua University,Beijing, China
Hideo Fujiwara , Nara Institute of Sci. and Technology, Japan
Mingjing Chen , Univ. of California, San Diego
pp. 126-131

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
Chaowen Yu , University of Iowa
pp. 132-137

Low Transition LFSR for BIST-Based Applications (Abstract)

Mohammad Tehranipoor , Univ. of Maryland Baltimore County
Nisar Ahmed , Texas Instruments
Mehrdad Nourani , Univ. of Texas at Dallas
pp. 138-143

A BIST Scheme Based on Selecting State Generation of Folding Counters (Abstract)

Cuiyun Jiang , Hefei University of Technology, China
Maoxiang Yi , Hefei University of Technology, China
Huaguo Liang , Hefei University of Technology, China
Xiangsheng Fang , Hefei University of Technology, China
pp. 144-149
Session A4: SoC Testing

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Tomokazu Yoneda , Nara Institute of Science and Technology
Hisakazu Takakuwa , RICOH, Japan
pp. 150-155

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression (Abstract)

Hiroyuki Nakamura , Kawasaki Microelectronics
Anis Uzzaman , Cadence Design Systems, Inc
Yoshihiko Terauchi , Innotech Corporation
Yoshihito Nishizaki , Kawasaki Microelectronics
Tsutomu Ube , Innotech Corporation
Vivek Chickermane , Cadence Design Systems, Inc
Akio Shirokane , Kawasaki Microelectronics
Brion Keller , Cadence Design Systems, Inc
pp. 156-161

SOC Test Scheduling with Test Set Sharing and Broadcasting (Abstract)

Anders Larsson , Linkopings Universitet, Sweden
Zebo Peng , Linkopings Universitet, Sweden
Petru Eles , Linkopings Universitet, Sweden
Erik Larsson , Linkopings Universitet, Sweden
pp. 162-169
Session B4: Yield Enhancement

Flash Memory Die Sort by a Sample Classification Method (Abstract)

Jen-Chieh Yeh , National Tsing Hua University, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Taiwan
Chia-Ching Wang , Winbond Electronics Corporation, Taiwan
Yung-Chen Lin , Winbond Electronics Corporation, Taiwan
Chao-Hsun Chen , Winbond Electronics Corporation, Taiwan
Yu-Chun Dawn , National Tsing Hua University, Taiwan
pp. 182-187

Chip Identification using the Characteristic Dispersion of Transistor (Abstract)

Tatsuya FURUKAWA , Matsushita Electric Industrial Co., Ltd.
Junichi HIRASE , Matsushita Electric Industrial Co., Ltd.
pp. 188-193
Session A5: Delay and Defect-Based Testing

Untestable Multi-Cycle Path Delay Faults in Industrial Designs (PDF)

Suriyaprakash Natarajan , Intel Corporation, Santa Clara, CA
Manan Syal , Virginia Tech, Blacksburg, VA
Sreejit Chakravarty , Intel Corporation, Santa Clara, CA
Michael S. Hsiao , Virginia Tech, Blacksburg, VA
pp. 194-201

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions (Abstract)

S. M. Reddy , University of Iowa, Iowa
I. Pomeranz , Purdue University
N. Devtaprasanna , University of Iowa, Iowa
A. Gunda , LSI Logic Corporation, Milpitas, CA
P. Krishnamurthy , LSI Logic Corporation, Milpitas, CA
pp. 202-207

Selection of Paths for Delay Testing (Abstract)

I-De Huang , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 208-215

On Improving Defect Coverage of Stuck-at Fault Tests (Abstract)

Kohei Miyase , Fukuoka, Japan Science and Technology Agency
Kenta Terashima , Kyushu Institute of Technology
Sudhakar M. Reddy , University of Iowa
Seiji Kajihara , Kyushu Institute of Technology
Xiaoqing Wen , Kyushu Institute of Technology
pp. 216-223
Session B5: Low Power Testing

A Scan Matrix Design for Low Power Scan-Based Test (Abstract)

Shih Ping Lin , National Chiao Tung University, Taiwan
Jwu E Chen , National Central University, Taiwan
Chung Len Lee , National Chiao Tung University, Taiwan
pp. 224-229

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture (Abstract)

Sungho Kang , Yonsei University, Korea
Yong Lee , Yonsei University, Korea
Youbean Kim , Yonsei University, Korea
Myung-Hoon Yang , Yonsei University, Korea
pp. 230-235

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing (Abstract)

Zainalabedin Navabi , University of Tehran, Iran
Hadi Esmaeilzadeh , University of Tehran, Iran
Pooya Saeedi , University of Tehran, Iran
Saeed Shamshiri , University of Tehran, Iran
pp. 236-241

Partial Gating Optimization for Power Reduction During Test Application (Abstract)

Mohammed ElShoukry , Univ. of Maryland Baltimore County
Mohammad Tehranipoor , Univ. of Maryland Baltimore County
C.P. Ravikumar , Texas Instruments India
pp. 242-247
Session A6: Diagnosis, Delay, and Defect-Based Testing

Bridge Defect Diagnosis with Physical Information (Abstract)

Sudhakar M. Reddy , University of Iowa
Wei Zou , University of Iowa
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR
pp. 248-253

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths (Abstract)

Yuki Yoshikaw , Nara Institute of Science and Technology, Japan
and Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Michiko Inoue , Nara Institute of Science and Technology, Japan
Satoshi Ohtake , Nara Institute of Science and Technology, Japan
pp. 254-259

A Class of Linear Space Compactors for Enhanced Diagnostic (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison, USA.
Thomas Clouqueur , Nara Institute of Science and Technology, Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 260-265

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing (Abstract)

Ilia Polian , Albert-Ludwigs-University, Germany
Bernd Becker , Albert-Ludwigs-University, Germany
Piet Engelke , Albert-Ludwigs-University, Germany
Sandip Kundu , University of Massachusetts, Amherst, MA
pp. 266-271
Session B6: Test Generation and Fault Simulation

Enhancing Fault Simulation Performance by Dynamic Fault Clustering (Abstract)

Zainalabedin Navabi , University of Tehran, Iran
Shahrzad Mirkhani , University of Tehran, Iran
pp. 278-283

Cost Optimal Design of Nonlinear CA based PRPG for Test Applications (Abstract)

H Rahaman , Bengal Engineering and Science University, Shibpur, Howrah, India
Sukanta Das , Bengal Engineering and Science University, Shibpur, Howrah, India
Biplab K Sikdar , Bengal Engineering and Science University, Shibpur, Howrah, India
pp. 284-287

An Effective Design for Hierarchical Test Generation Based on Strong Testability (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Hideyuki Ichihara , Faculty of Information Sciences Hiroshima City University
Tomoo Inoue , Faculty of Information Sciences Hiroshima City University
Naoki Okamoto , Graduate School of Information Sciences Hiroshima City University
Toshinori Hosokawa , College of Industrial Technology Nihon University
pp. 288-293

Concurrent Test Generation (Abstract)

Vishwani D , Auburn University, USA
D. Agrawal , Auburn University, USA
Alok S. Doshi , Auburn University, USA
pp. 294-299
Session A7: Design for Testability

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Hiroyuki Iwata , Nara Institute of Science and Technology, Japan
Satoshi Ohtake , Nara Institute of Science and Technology, Japan
Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
pp. 306-311

Achieving High Test Quality with Reduced Pin Count Testing (Abstract)

Nilanjan Mukherjee , Mentor Graphics Corporation,Wilsonville, OR
Ron Press , Mentor Graphics Corporation,Wilsonville, OR
Jay Jahangiri , Mentor Graphics Corporation,Wilsonville, OR
Wu-Tung Cheng , Mentor Graphics Corporation,Wilsonville, OR
Subramanian Mahadevan , Mentor Graphics Corporation,Wilsonville, OR
pp. 312-317

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops (Abstract)

Dong Xiang , Tsinghua University, China
Kai wei Li , Tsinghua University, China
Hideo Fujiwara , Nara Institute of Science and Technology, Japan
pp. 318-323
Session B7: Test Compression and Compaction

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing (Abstract)

Jwu E Chen , National Central University, Taiwan
Chung Len Lee , National Chiao Tung University, Taiwan
Shih Ping Lin , National Chiao Tung University, Taiwan
pp. 324-329

Efficient Test Compaction for Pseudo-Random Testing (Abstract)

Sheng Zhang , University of Nebraska-Lincoln, USA
Bhargab B. Bhattacharya , ACM Unit Indian Statistical Institute Calcutta
Sharad C. Seth , University of Nebraska-Lincoln, USA
pp. 337-342

Test Data Compression with Partial LFSR-Reseeding (Abstract)

Sying-Jyan Wang , National Chung-Hsing University, Taichung, Taiwan
Yu-Hsuan Fu , National Chung-Hsing University, Taichung, Taiwan
pp. 343-347
Session A8: Design for Testability: II

CryptoScan: A Secured Scan Chain Architecture (Abstract)

S. Banerjee , Indian Institute of Technology Kharagpur, India
D. Mukhopadhyay , Indian Institute of Technology Kharagpur, India
B. B. Bhattacharya , Indian Institute of Technology Kharagpur, India
D. RoyChowdhury , Indian Institute of Technology Kharagpur, India
pp. 348-353

Pseudo-Parity Testing with Testable Design (Abstract)

Shiyi Xu , Shanghai University, China
pp. 354-359

Finite State Machine Synthesis for At-Speed Oscillation Testability (Abstract)

Katherine Shu-Min Li , National Chiao Tung University, Hsichu, Taiwan
Chauchin Su , National Chiao Tung University, Hsichu, Taiwan
Chung Len Lee , National Chiao Tung University, Hsichu, Taiwan
Tagin Jiang , National Chiao Tung University, Hsichu, Taiwan
Jwu E. Chen , National Central University, Chungli, Taiwan
pp. 360-365

A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture (Abstract)

Tsuyoshi Shinogi , Mie University, Tsu, Mie, JAPAN
Hiroyuki Yamada , Mie University, Tsu, Mie, JAPAN
Terumine Hayashi , Mie University, Tsu, Mie, JAPAN
Tomohiro Yoshikawa , Nagoya University, Nagoya, JAPAN
Shinji Tsuruoka , Mie University, Tsu, Mie, JAPAN
pp. 366-371
Session B8: Test Compression, Test Compaction, and Defect-Based Testing

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor (Abstract)

Xiaowei Li , Computing Technology, Chinese Academy of Sciences, Beijing, China
Yinhe Han , Computing Technology, Chinese Academy of Sciences, Beijing, China
Shivakumar Swaminathan , IBM Microelectronics, Research Triangle Park, NC
Yu Hu , Computing Technology, Chinese Academy of Sciences, Beijing, China
Anshuman Chandra , Synopsys, Inc. Mountain View, CA
pp. 372-377

Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation (Abstract)

S. Saqib Khursheed , King Fahd University, Saudi Arabia
Aiman H. El-Maleh , King Fahd University, Saudi Arabia
Sadiq M. Sait , King Fahd University, Saudi Arabia
pp. 378-385

Low Power Test Compression Technique for Designs with Multiple Scan Chain (Abstract)

Nozomu Togawa , Waseda University, Japan
Shinji Kimura , Grad. School of Infomation, Production and Systems, Waseda University, Japan
Youhua Shi , Waseda University, Japan
Tatsuo Ohtsuki , Waseda University, Japan
Masao Yanagisawa , Waseda University, Japan
pp. 386-389

Threshold testing: Covering bridging and other realistic faults (Abstract)

Sandeep K. Gupta , University of Southern California
Zhigang Jiang , SynTest Technologies, Inc. Sunnyvale CA
pp. 390-397
Session A9: Design for Testability: III

Synthesis of Testable Finite State Machine Through Decomposition (Abstract)

Arijit Sarkar , Bengal Eng. and Science Univ., Shibpur, India
DeBesh K Das , Jadavpur University, India
S Roy , National Institute of Teachers' Training and Research, India
Biplab K Sikdar , Bengal Eng. and Science Univ., Shibpur, India
pp. 398-403

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability (Abstract)

K. Roy , Purdue University, IN
S. Ghosh , Purdue University, IN
S. Bhunia , Purdue University, IN
pp. 404-409

Flip-flop chaining architecture for power-efficient scan during test application (Abstract)

Santanu Chattopadhyay , Electrical Communication Engineering,IIT Kharagpur, West Bengal
Tarang Vaish , IIT Guwahati North Guwahati, Assam
Shantanu Gupta , IIT Guwahati North Guwahati, Assam
pp. 410-413

A Unified Approach to Partial Scan Design using Genetic Algorithm (Abstract)

Indranil Sengupta , Indian Institute of Technology, Kharagpur, India
Varun Arora , Indian Institute of Technology, Kharagpur, India
pp. 414-421
Session B9: Fault Modeling, Processor Testing, and Memory Testing

A Family of Logical Fault Models for Reversible Circuits (Abstract)

Thomas Fiehn , Albert-Ludwigs-University, Germany
Ilia Polian , Albert-Ludwigs-University, Germany
John P. Hayes , University of Michigan, USA
Bernd Becker , Albert-Ludwigs-University, Germany
pp. 422-427

Compressing Functional Tests for Microprocessors (Abstract)

Kedarnath J. Balakrishnan , NEC Labs. America, Princeton, NJ
Nur A. Touba , University of Texas at Austin
Srinivas Patil , Intel Corporation, Austin, TX
pp. 428-433

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach (Abstract)

Said Hamdioui , Delft University of Technology, The Netherlands
Zaid Al-Ars , Delft University of Technology, The Netherlands
Jorg Vollrath , Infineon Technologies AG, Munich, Germany
pp. 434-439

Arithmetic Test Strategy for FFT Processor (Abstract)

Guang-Ju Chen , University of Electronic Science and Technology of China
Ji-Xue Xiao , University of Electronic Science and Technology of China
Yong-Le Xie , University of Electronic Science and Technology of China
pp. 440-443

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation (Abstract)

Tsuyoshi Iwagaki , Japan Advanced Institute of Science and Technology
Michiko Inoue , Nara Institute of Science and Technology, Kansai Science City , Japan
Hideo Fujiwara , Nara Institute of Science and Technology, Kansai Science City , Japan
Kazuko Kambe , Nara Institute of Science and Technology, Kansai Science City , Japan
pp. 444-449
Session C1: SoC Test Practices

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing (PDF)

Maurice Lousberg , Philips Research Laboratories, The Netherlands
Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Tom Waayers , Philips Research Laboratories, The Netherlands
pp. 450

DFT for Low Cost SOC Test (PDF)

Rubin A. Parekhji , Texas Instruments (India) Pvt. Ltd.
pp. 451
Session C2: Defect-Based Testing

The Ultimate Chase (PDF)

Prabhu Krishnamurthy , LSI Logic Corp.
pp. 454

Defect-Oriented Test for Ultra-Low DPM (PDF)

Vikram Iyengar , IBM Microelectronics, US
Phil Nigh , IBM Microelectronics, US
pp. 455
Session C4: Advances in Test Generation and Verification

High Level Test Generation for Custom Hardware: An Industrial Perspective (PDF)

Indradeep Ghosh , Fujitsu Laboratories of America, Sunnyvale, CA
pp. 458

Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes (PDF)

Subramanian Iyer , Univ. of Texas at Austin, TX
Takeshi Shimizu , Stanford University, CA
Debashis Sahoo , Fujitsu Laboratories of America, USA
Jawahar Jain , Univ. of Texas at Austin, TX
pp. 460
Session C5: Test Data Compression and System Level Testing

Emerging Techniques for Test Data Compression (PDF)

Kedarnath J. Balakrishnan , NEC Laboratories America, Princeton, NJ
pp. 462

Improving Test Quality Using Test Data Compression (PDF)

Nilanjan Mukherjee , Mentor Graphics Corporation,Wilsonville, OR
pp. 463
Session C6: Mixed Signal Testing

Challenges in Next Generation Mixed-Signal IC Production Testing (PDF)

Sasikumar Cherubal , Test Engineering, Wiquest Communications
pp. 466

Practices in Testing of Mixed-Signal and RF SoCs (PDF)

Salem Abdennadher , Intel Corporation, Folsom, CA
Saghir A Shaikh , Sun Microsystems, San Diego, CA
pp. 467

Challenges in High Speed Interface Testing (PDF)

Salem Abdennadher , Intel Corporation, Folsom, CA
Saghir A Shaikh , Sun Microsystems, San Diego, CA
pp. 468
Session C7: Delay Testing and Burn-in Test Methodologies

Practical Aspects of Delay Testing for Nanometer Chips (PDF)

Brion Keller , Cadence Design Systems, Endicott, NY
Kevin McCauley , Cadence Design Systems, Endicott, NY
Anis Uzzaman , Cadence Design Systems, Endicott, NY
Vivek Chickermane , Cadence Design Systems, Endicott, NY
pp. 470

Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST (PDF)

Zainal Abu Kassim , Freescale Semiconductor, Selangor, Malaysia
Serge Demidenko , Monash University Malaysia
Fairuz Zakaria , Freescale Semiconductor, Selangor, Malaysia
Melanie Po-Leen Ooi , Monash University Malaysia
pp. 472
Author Index

Author Index (PDF)

pp. 473
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