The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2004)
Kenting, Taiwan
Nov. 15, 2004 to Nov. 17, 2004
ISSN: 1081-7735
ISBN: 0-7695-2235-1
TABLE OF CONTENTS
Introduction

Keynote speech (PDF)

pp. xix-xx

Foreword (PDF)

pp. xi

Invited Talk (Abstract)

pp. xxi

TTTC Introduction (PDF)

pp. xxii-xxiv

TTEP Introduction (PDF)

pp. xxvi
Introduction

Foreword (PDF)

pp. xi

Organizing Committee (PDF)

pp. xii-xiii

Tutorials (PDF)

pp. xvi-xviii
Session A1: SOC Testing

null (PDF)

pp. null

Multi-Frequency Test Access Mechanism Design for Modular SOC Testing (Abstract)

Qiang Xu , McMaster University
Nicola Nicolici , McMaster University
pp. 2-7

Rapid and Energy-Efficient Testing for Embedded Cores (Abstract)

Huawei Li , Chinese Academy of Science
Anshuman Chandra , Synopsys, Inc.
Yu Hu , Chinese Academy of Science
Xiaowei Li , Chinese Academy of Science
Yinhe Han , Chinese Academy of Science
pp. 8-13

Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy (Abstract)

Jianhui Xing , Tsinghua University
Hong Wang , Tsinghua University
Shiyuan Yang , Tsinghua University
pp. 14-19

Adding Testability to an Asynchronous Interconnect for GALS SoC (Abstract)

Aristides Efthymiou , University of Manchester
Douglas A. Edwards , University of Manchester
John Bainbridge , University of Manchester
pp. 20-23
Session B1: Low-Power Testing

null (PDF)

pp. null

Test Power Reduction with Multiple Capture Orders (Abstract)

Shaing-Jer Hsu , National Cheng Kung University
Kuen-Jong Lee , National Cheng Kung University
Chia-Ming Ho , National Cheng Kung University
pp. 26-31

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths (Abstract)

Ken?ichi Yamaguchi , Nara National College of Technology
Michiko Inoue , Nara Institute of Science and Technology
Zhiqiang You , Nara Institute of Science and Technology
Jacob Savir , New Jersey Institute of Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 32-39

Low Power BIST with Smoother and Scan-Chain Reorder (Abstract)

Sying-Jyan Wang , National Chung-Hsing University
Nan-Cheng Lai , National Chung-Hsing University
Yu-Hsuan Fu , National Chung-Hsing University
pp. 40-45
Session C1: Analog BIST

null (PDF)

pp. null

A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters (Abstract)

Soon-Jyh Chang , National Cheng Kung University
Hsin-Wen Ting , National Cheng Kung University
Bin-Da Liu , National Cheng Kung University
pp. 52-57

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC (Abstract)

Chung-Len Lee , National Chiao Tung University
Jwu-E Chen , National Chung Hua University
Guan-Xun Chen , National Chiao Tung University
pp. 58-61

A Σ-Δ Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose (Abstract)

Hao-Chiao Hong , National Chiao Tung University
Cheng-Wen Wu , National Tsing-Hua University
Kwang-Ting Cheng , University of California at Santa Barbara
pp. 62-67
Session A2: Advanced DFT

null (PDF)

pp. null

Multiple Scan Tree Design with Test Vector Modification (Abstract)

Seiji Kajihara , Kyushu Institute of Technology
Kohei Miyase , Kyushu Institute of Technology
Sudhakar M. Reddy , University of Iowa
pp. 76-81

An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains (Abstract)

Ching-Hsiu Lin , Tamkang University
Jun-Yi Chang , Tamkang University
Jiann-Chyi Rau , Tamkang University
pp. 82-87

Scan-Based BIST Using an Improved Scan Forest Architecture (Abstract)

Kai-wei Li , Tsinghua University
Dong Xiang , Tsinghua University
Ming-jing Chen , Tsinghua University
Yu-liang Wu , Chinese University of Hong Kong
pp. 88-93

The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time (Abstract)

Il-soo Lee , University of Texas at Austin
Tony Ambler , University of Texas at Austin
Yong Min Hur , Dong Seoul College
pp. 94-97
Session B2: Fault Analysis

null (PDF)

pp. null

Testing for Missing-Gate Faults in Reversible Circuits (Abstract)

Bernd Becker , Albert-Ludwigs-University
Ilia Polian , Albert-Ludwigs-University
John P. Hayes , University of Michigan and Albert-Ludwigs-University
pp. 100-105

Properties of Maximally Dominating Faults (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 106-111

I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment (Abstract)

Masaki Hashizume , University of Tokushima
Takeshi Koyama , Tokushima Bunri University
Tetsuo Tada , Tokushima Bunri University
Ikuro Morita , University of Tokushima
Daisuke Yoneda , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
Takeomi Tamesada , University of Tokushima
pp. 112-117

High Level Fault Injection for Attack Simulation in Smart Cards (Abstract)

A. Muehlberger , Philips Semiconductors
U. Neffe , Graz University of Technology
E. Rieger , Philips Semiconductors
R. Weiss , Graz University of Technology
K. Rothbart , Graz University of Technology
Ch. Steger , Graz University of Technology
pp. 118-121
Session C2: Cross-Talk Testing

null (PDF)

pp. null

Efficient Identification of Crosstalk Induced Slowdown Targets (Abstract)

Shahin Nazarian , University of Southern California
Sandeep K. Gupta , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 124-131

A New Path Delay Test Scheme Based on Path Delay Inertia (Abstract)

Chung Liang Chen , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
Ming-Shae Wu , National Chiao Tung University
pp. 140-144

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI (Abstract)

Katherine Shu-Min Li , National Chiao Tung University
Jwu E Chen , National Central University
Chung Len Lee , National Chiao Tung University
Chauchin Su , National Chiao Tung University
pp. 145-150
Session A3: Functional Testing

null (PDF)

pp. null

Efficient Template Generation for Instruction-Based Self-Test of Processor Cores (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Kazuko Kambe , Nara Institute of Science and Technology
Michiko Inoue , Nara Institute of Science and Technology
pp. 152-157

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores (Abstract)

Zainalabedin Navabi , University of Tehran
Saeed Shamshiri , University of Tehran
Hadi Esmaeilzadeh , University of Tehran
pp. 158-163

A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA (Abstract)

Chin-Lung Chuang , National Central University
Dong-Jung Lu , National Central University
Chien-Nan Jimmy Liu , National Central University
pp. 164-169

A Systematic Way of Functional Testing for VLSI Chips (Abstract)

Shiyi Xu , Shanghai University
pp. 170-175
Session B3: Logic BIST

null (PDF)

pp. null

Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults (Abstract)

Chaowen Yu , University of Iowa
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 178-183

A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool (Abstract)

Amit Patra , Indian Institute of Technology at Kharagpur
Santosh Biswas , Indian Institute of Technology at Kharagpur
Siddhartha Mukhopadhyay , Indian Institute of Technology at Kharagpur
pp. 184-189

Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters (Abstract)

Kenichi Ichino , Tokyo Metropolitan University
Kazuhiko Iwasaki , Tokyo Metropolitan University
Satoshi Fukumoto , Tokyo Metropolitan University
Harunobu Kurokawa , Tokyo Metropolitan University
Masayuki Arai , Tokyo Metropolitan University
pp. 190-195

Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults (Abstract)

Anirban Kundu , Bengal Engineering College
Biplad K. Sikdar , Bengal Engineering College
Sukanta Das , Bengal Engineering College
pp. 196-201
Session C3: Fault Diagnosis

null (PDF)

pp. null

Compactor Independent Direct Diagnosis (Abstract)

Nagesh Tamarapalli , Mentor Graphics Corporation
Kun-Han Tsai , Mentor Graphics Corporation
Yu Huang , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Janusz Rajski , Mentor Graphics Corporation
pp. 204-209

Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits (Abstract)

W. B. Jone , University of Cincinnati
S. C. Chang , National Tsing-Hua University
K. W. Lai , Broadcom Corporation
S. Ghosh , University of Cincinnati
pp. 210-215

Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set (Abstract)

Yoshinobu Higami , Ehime University
Hiroshi Takahashi , Ehime University
Yuzo Takamatsu , Ehime University
Yukihiro Yamamoto , Ehime University
pp. 216-221

Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests (Abstract)

Yuzo Takamatsu , Ehime University
Yuichi Sato , Ehime University
Hiroshi Takahashi , Ehime University
Yoshinobu Higami , Ehime University
pp. 222-227
Session A4: SOC Test Scheduling

null (PDF)

pp. null

Hybrid BIST Test Scheduling Based on Defect Probabilities (Abstract)

Gert Jervan , Link?ping University
Zhiyuan He , Link?ping University
Petru Eles , Link?ping University
Zebo Peng , Link?ping University
pp. 230-235

Pair Balance-Based Test Scheduling for SOCs (Abstract)

Hua-Wei Li , Chinese Academy of Science
Yu Hu , Chinese Academy of Science
Yin-He Han , Chinese Academy of Science
Tao Lv , Chinese Academy of Science
Xiao-Wei Li , Chinese Academy of Science
pp. 236-241

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test (Abstract)

Sunghoon Chun , Yonsei University
Jung-Been Im , Yonsei University
Geunbae Kim , Yonsei University
Sungho Kang , Yonsei University
Jin-Ho An , Yonsei University
pp. 242-247

March Based Memory Core Test Scheduling for SOC (Abstract)

Wei-Lun Wang , Cheng Shiu University
pp. 248-253
Session B4: Memory Testing

null (PDF)

pp. null

On Test and Diagnostics of Flash Memories (Abstract)

Jen-Chieh Yeh , National Tsing Hua University
Yuan-Yuan Shih , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Rei-Fu Huang , National Tsing Hua University
pp. 260-265

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution (Abstract)

Luigi Dilillo , Université de Montpellier 11/ CNRS
Serge Pravossoudovitch , Université de Montpellier 11/ CNRS
Arnaud Virazel , Université de Montpellier 11/ CNRS
Magali Hage-Hassan , Infineon Technologies France
Patrick Girard , Université de Montpellier 11/ CNRS
Simone Borri , Infineon Technologies France
pp. 266-271

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier (Abstract)

Tsin-Yuan Chang , National Tsing Hua University
Ming-Jun Hsiao , National Tsing Hua University
Yi-Ming Sheng , National Tsing Hua University
pp. 272-276

An Efficient Diagnosis Scheme for Random Access Memories (Abstract)

Chao-Da Huang , National Central University
Jin-Fu Li , National Central University
pp. 277-282

Evaluation of Intra-Word Faults in Word-Oriented RAMs (Abstract)

Zaid Al-ars , Delft University of Technology and CatRam Solutions
Said Hamdioui , Delft University of Technology and Currently with Philips Semiconductor Crolles R&D
John D. Reyes , Intel Corporation
pp. 283-288
Session C4: Analog Testing

null (PDF)

pp. null

A Low-Cost Diagnosis Methodology for Pipelined A/D Converters (Abstract)

Soon-Jyh Chang , National Cheng Kung University
Kuen-Jong Lee , National Cheng Kung University
Chih-Haur Huang , National Cheng Kung University
pp. 296-301

Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits (Abstract)

Shalabh Goyal , Georgia Institute of Technology
Ganesh Srinivasan , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 302-307

Dynamic Analog Testing via ATE Digital Test Channels (Abstract)

C. S. Chang , National Chiao Tung University
C. L. Lee , National Chiao Tung University
Jerry C. H. Lin , SynTest Technologies, Inc.
H. W. Huang , National Chiao Tung University
D. S. Tu , National Chiao Tung University
C. C. Su , National Chiao Tung University
pp. 308-312
Session A5: Testable Design

null (PDF)

pp. null

Design and Implementation of Self-Testable Full Range Window Comparator (Abstract)

Mike W. T. Wong , Hong Kong Polytechnic University
Yubin Zhang , Hong Kong Polytechnic University
pp. 314-318

Efficient Test Methodologies for Conditional Sum Adders (Abstract)

Chih-Chiang Hsu , National Central University
Jin-Fu Li , National Central University
pp. 319-324

A Novel Approach for On-line Testable Reversible Logic Circuit Design (Abstract)

J. P. Parkerson , University of Arkansas
P. K. Lala , University of Arkansas
D. P. Vasudevan , University of Arkansas
pp. 325-330

Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores (Abstract)

Sukanta Das , Bengal Engineering College
P Pal Chaudhuri , Flat E4
Biplab K. Sikdar , Bengal Engineering College
pp. 331-334
Session B5: Testability Analysis

null (PDF)

pp. null

Circuit-Width Based Heuristic for Boolean Reasoning (Abstract)

Xiaowei Li , Chinese Academy of Sciences
Guanghui Li , Zhejiang Forestry College and Chinese Academy of Sciences
pp. 336-341

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity (Abstract)

Debesh Kumar Das , Jadavpur University
Hideo Fujiwara , Nara Institute of Science and Technology
Tomoo Inoue , Hiroshima City University
Susanta Chakraborty , Kalyani University
pp. 342-347

Classification of Sequential Circuits Based on τk Notation (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Chia Yee Ooi , Nara Institute of Science and Technology
pp. 348-353

A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits (Abstract)

Shiy Xu , Shanghai University
E. Edirisuriya , University of Sri Jayewardenepura
pp. 354-357
Session C5: Yield and Reliability

null (PDF)

pp. null

Burn-In Stress Test of Analog CMOS ICs (Abstract)

Chin-Long Wey , National Central University
Meng-Yao Liu , National Central University
pp. 360-365

Fail Pattern Identification for Memory Built-In Self-Repair (Abstract)

Kun-Lun Luo , Industrial Technology Research Institute
Shen-Tien Lin , Industrial Technology Research Institute
Cheng-Wen Wu , National Tsing Hua University
Yeong-Jar Chang , Industrial Technology Research Institute
Chin-Lung Su , National Tsing Hua University
Rei-Fu Huang , National Tsing Hua University
pp. 366-371

Reduce Yield Loss in Delay Defect Detection in Slack Interval (Abstract)

Adit D. Singh , Auburn University
Haihua Yan , Auburn University
pp. 372-377

Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing (Abstract)

Chuan-Ching Sue , National Cheng Kung University
Chin-Yu Huang , National Tsing Hua University
Chu-Ti Lin , National Tsing Hua University
pp. 378-383
Session A6: Fault Tolerance

null (PDF)

pp. null

Intelligible Test Techniques to Support Error-Tolerance (Abstract)

Melvin A. Breuer , University of Southern California
pp. 386-393

Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion (Abstract)

Jun-Ying Yeh , National Cheng Kung University
Chuan-Ching Sue , National Cheng Kung University
Chin-Yu Huang , National Tsing Hua University
pp. 400-405

On Improvement in Fault Tolerance of Hopfield Neural Networks (Abstract)

Teijiro Isokawa , University of Hyogo
Nobuyuki Matsui , University of Hyogo
Naotake Kamiura , University of Hyogo
pp. 406-411
Session B6: FPGA Testing and Test Reduction

null (PDF)

pp. null

Testing and Diagnosis Techniques for LUT-Based FPGA?s (Abstract)

Shyue-Kung Lu , Fu Jen Catholic University
Yu-Cheng Tsai , Fu Jen Catholic University
Shoei-Jia Yan , Fu Jen Catholic University
Hung-Chin Wu , Fu Jen Catholic University
pp. 414-419

Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Donghoon Han , Georgia Institute of Technology
pp. 420-425

A Test Decompression Scheme for Variable-Length Coding (Abstract)

Hideyuki Ichihara , Hiroshima City University
Tomoo Inoue , Hiroshima City University
Michihiro Shintani , Hiroshima City University
Masakuni Ochi , Hiroshima City University
pp. 426-431
Session C6: Delay Testing

null (PDF)

pp. null

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects (Abstract)

Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
Lei Wang , University of Southern California
pp. 440-447

Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing (Abstract)

Nicola Nicolici , McMaster University
Ho Fai Ko , McMaster University
pp. 454-459

Analysis and Attenuation Proposal in Ground Bounce (Abstract)

Florence Azais , Laboratoire déInformatique, Robotique et de Microélectronique de Montpellier-LIRMM
Antonio Zenteno , National Institute for Astrophysics Optics and Electronics-INAOE
Victor H. Champac , National Institute for Astrophysics Optics and Electronics-INAOE
Michell Renovell , Laboratoire déInformatique, Robotique et de Microélectronique de Montpellier-LIRMM
pp. 460-463
Author Index

Author Index (PDF)

pp. 464-465
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