2012 IEEE 21st Asian Test Symposium (2004)
Nov. 15, 2004 to Nov. 17, 2004
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.2004.20
Aristides Efthymiou , University of Manchester
Douglas A. Edwards , University of Manchester
John Bainbridge , University of Manchester
Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used as an example. Test patterns are generated by a custom program automatically, given the topology of the interconnect. In comparison to standard, asynchronous, full-scan LSSD methods, area savings in the order of 50% are noted.
Aristides Efthymiou, Douglas A. Edwards, John Bainbridge, "Adding Testability to an Asynchronous Interconnect for GALS SoC", 2012 IEEE 21st Asian Test Symposium, vol. 00, no. , pp. 20-23, 2004, doi:10.1109/ATS.2004.20