The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2003)
Xi?an, China
Nov. 16, 2003 to Nov. 19, 2003
ISSN: 1081-7735
ISBN: 0-7695-1951-2
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. xxi
Plenary Session: Keynote Address
Session 1A: Design for Testability

null (PDF)

pp. null

Reducing Scan Shifts Using Folding Scan Trees (Abstract)

Hiroyuki Yotsuyanagi , University of Tokushima
Shigeki Nishikawa , Sharp Corporation
Masaki Hashizume , University of Tokushima
Toshimasa Kuchii , Sharp Corporation
Kozo Kinoshita , Osaka Gakuin University
pp. 6

Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning (Abstract)

Dong Xiang , Tsinghua University
Jia-Guang Sun , Tsinghua University
Hideo Fujiwara , Nara Institute of Science and Technology
Ming-Jing Chen , Tsinghua University
pp. 12

IC Reliability Simulator ARET and Its Application in Design-for-Reliability (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Mark T. Chisa , The Boeing Company
Adit D. Singh , Auburn University
Xiangdong Xuan , Georgia Institute of Technology
Namsoo P. Kim , The Boeing Company
pp. 18
Session 1B: Memory Testing 1

null (PDF)

pp. null

Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces (Abstract)

Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 24

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells (Abstract)

Takashi Murai , INNOTECH Corp.
Kazuhiko Iwasaki , Tokyo Metropolitan University
Nobuyuki Otsuka , INNOTECH Corp.
Kenichi Ichino , Tokyo Metropolitan University
Satoshi Fukumoto , Tokyo Metropolitan University
Masayuki Sato , INNOTECH Corp.
Masayuki Arai , Tokyo Metropolitan University
Yuki Yamagata , Tokyo Metropolitan University
Hiroyuki Itabashi , INNOTECH Corp.
pp. 28

Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool (Abstract)

F. Bertuccelli , Aurelia Microelettronica S.p.A
G. Di Natale , Politecnico di Torino
F. Bigongiari , Aurelia Microelettronica S.p.A
R. Saletti , Universit? di Pisa
P. Prinetto , Politecnico di Torino
A. S. Brogna , Universit? di Pisa
pp. 32
Session 1C: Fault Diagnosis 1

null (PDF)

pp. null

Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults (Abstract)

Yu-Chiun Lin , National Tsing-Hua University
Shi-Yu Huang , National Tsing-Hua University
pp. 38

Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults (Abstract)

Yu-Ting Hung , Faraday Technology Corporation
Cheng-Ju Hsieh , Faraday Technology Corporation
Yu Huang , Mentor Graphics Corporation
Huan-Yung Tseng , Faraday Technology Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Alou Huang , Faraday Technology Corporation
pp. 44
Session 2A: Delay Testing

null (PDF)

pp. null

Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models (Abstract)

Satoshi Ohtake , Nara Institute of Science and Technology
Tsuyoshi Iwagaki , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 58

On Estimation of Fault Efficiency for Path Delay Faults (Abstract)

Sadami Takeoka , Matsushita Electric Industrial Co., Ltd. Semiconductor Company
Seiji Kajihara , Kyushu Institute of Technology
Masayasu Fukunaga , Kyushu Institute of Technology
pp. 64

Software-Based Delay Fault Testing of Processor Cores (Abstract)

Virendra Singh , Nara Institute of Science and Technology and Central Electronics Engineering Research Institute
Michiko Inoue , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
Kewal K Saluja , University of Wisconsin-Madison
pp. 68
Session 2B: BIST

null (PDF)

pp. null

Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity (Abstract)

Biplab K. Sikdar , Bengal Engineering College
Sukanta Das , Bengal Engineering College
Subhayan Sen , Bengal Engineering College
P. Pal Chaudhuri , Bengal Engineering College
Anirban Kundu , Bengal Engineering College
pp. 78
Session 2C: Software Testing 1

null (PDF)

pp. null

Domain Testing Based on Character String Predicate (Abstract)

Yinghua Min , Chinese Academy of Sciences in Beijing
Ruilian Zhao , Beijing University of Chemical Technology
Michael R. Lyu , Chinese University of Hong Kong
pp. 96

Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains (Abstract)

Fenhua Zhen , University of Erlangen-Nuremberg
Winfried Dulz , University of Erlangen-Nuremberg
Matthias Beyer , University of Erlangen-Nuremberg
pp. 102

An Expression?s Single Fault Model and the Testing Methods (Abstract)

Xiaowei Li , Chinese Academy of Science
Yunzhan Gong , Academy of Armored Forces Engineering Beijing
Wanli Xu , Academy of Armored Forces Engineering Beijing
pp. 110
Session 3A: Mixed-Signal Testing

null (PDF)

pp. null

PLL Based High Speed Functional Testing (Abstract)

Jayasanker Jayabalan , National University of Singapore
Mahadevan K. Iyer , Institute of Microelectronics
Chee Kiang Goh , Infineon Technologies
Andrew A.O. Tay , National University of Singapore
Ooi Ban Leong , National University of Singapore
Leong Mook Seng , National University of Singapore
pp. 116

A Sigma-Delta Modulation Based BIST Scheme for A/D Converters (Abstract)

Kuen-Jong Lee , National Cheng Kung University
Ruei-Shiuan Tzeng , National Cheng Kung University
Soon-Jyh Chang , National Cheng Kung University
pp. 124
Session 3B: Test Compaction 1

null (PDF)

pp. null

Optimal Scan Tree Construction with Test Vector Modification for Test Compression (Abstract)

Seiji Kajihara , Kyusyu Institute of Technology and Kyushu Institute of Technology
Kohei Miyase , Kyusyu Institute of Technology
pp. 136
Session 3C: RTL Verification

null (PDF)

pp. null

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG (PDF)

Indradeep Ghosh , Fujitsu Laboratories of America Inc.
Michael Hsiao , Virginia Tech
Liang Zhang , Virginia Tech
pp. 148

An Automatic Circuit Extractor for RTL Verification (Abstract)

Yang Guo , National University of Defense Technology
Tun Li , National University of Defense Technology
Sikun Li , National University of Defense Technology
pp. 154

An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains (Abstract)

Xiaowei Li , Chinese Academy of Sciences
Tao Lv , Chinese Academy of Sciences
Jianping Fan , Chinese Academy of Sciences
pp. 161
Session 4A: Enhanced Delay Testing and ATPG

null (PDF)

pp. null

Delay Testing of MOS Transistor with Gate Oxide Short (Abstract)

Y. Bertrand , Universit? de Montpellier II
F. Aza? , Universit? de Montpellier II
J.M. Galli?re , Universit? de Montpellier II
M. Renovell , Universit? de Montpellier II
pp. 168

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults (Abstract)

Sandeep K. Gupta , University of Southern California
Arani Sinha , University of Southern California
Melvin A. Breuer , University of Southern California
pp. 174

Delay Test Pattern Generation Considering Crosstalk-Induced Effects (Abstract)

Xiaowei Li , Chinese Academy of Sciences
Huawei Li , Chinese Academy of Sciences
Yue Zhang , Academy of Armored Forces Engineering
pp. 178

Automated Test Model Generation from Switch Level Custom Circuits (Abstract)

Jing Zeng , Motorola, Inc.
Magdy S. Abadir , Motorola, Inc.
Juhong Zhu , Sun Microsystem
Carol Pyron , Motorola, Inc.
pp. 184
Session 4B: Test Power

null (PDF)

pp. null

Power Conscious BIST Design for Sequential Circuits Using ghost-FSM (Abstract)

S Roy , Kalyani Govt. Engineering College
Biplab K Sikdar , Bengal Engineering College
pp. 190

Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits (Abstract)

Zhiguo Chen , Chinese Academy of Sciences and University of Electronic Science and Technology of China
Xiaowei Li , Chinese Academy of Sciences
Yongjun Xu , Chinese Academy of Sciences
Zuying Luo , Tsinghua University
pp. 196

Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test (Abstract)

Ozgur Sinanoglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 202
Session 4C: Software Testing 2

null (PDF)

pp. null

Conformance Test of Distributed Transaction Service (Abstract)

Chang Xu , Chinese Academy of Sciences
Beihong Jin , Chinese Academy of Sciences
pp. 216

Build-In-Self-Test for Software (Abstract)

Shiyi Xu , Shanghai University
pp. 220

Testing the Conformity of Transactional Attributes of Components by Simulation (Abstract)

Hui-Qun Zhao , China University Technology
Yuan Gao , Northeastern University
Qin-Xin Gao , Northeastern University
pp. 224
Session 5A: Fault Diagnosis 2

null (PDF)

pp. null

Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information (Abstract)

Alex Orailoglu , University of California at San Diego
Baris Arslan , University of California at San Diego
pp. 230

Fault Diagnosis for Physical Defects of Unknown Behaviors (Abstract)

Hideo Tamamoto , Akita University
Kewal K. Saluja , University of Wisconsin-Madison
Kozo Kinoshita , Osaka Gakuin University
Xiaoqing Wen , SynTest Technologies, Inc.
pp. 236
Session 5B: Memory Testing 2

null (PDF)

pp. null

Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders (Abstract)

Luigi Dilillo , Universit? de Montpellier II / CNRS
Simone Borri , Infineon Technologies France
Serge Pravossoudovitch , Universit? de Montpellier II / CNRS
Patrick Girard , Universit? de Montpellier II / CNRS
Arnaud Virazel , Universit? de Montpellier II / CNRS
pp. 250

Defect Oriented Fault Analysis for SRAM (Abstract)

Rei-Fu Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Yung-Fa Chou , National Tsing Hua University
pp. 256

A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs (Abstract)

Aditya S. Ramani , Indian Institute of Technology-Madras
V. Kamakoti , Indian Institute of Technology-Madras
Amol J. Mupid , Indian Institute of Technology-Madras
L. Kalyan Kumar , Indian Institute of Technology-Madras
pp. 262
Session 5C: SOC Test

null (PDF)

pp. null

Between-Core Vector Overlapping for Test Cost Reduction in Core Testing (Abstract)

Yuki Yamada , Mie University
Tsuyoshi Shinogi , Mie University
Tomohiro Yoshikawa , Mie University
Shinji Tsuruoka , Mie University
Terumine Hayashi , Mie University
pp. 268

A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores (Abstract)

Zhigang Jiang , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 278
Session 6A: DFT Synthesis

null (PDF)

pp. null

Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability (Abstract)

Debesh K. Das , Jadavpur University
Hafizur Rahaman , WB University of Technology
Bhargab B. Bhattacharya , Indian Statistical Institute
pp. 284

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability (Abstract)

Junhao Shi , University of Bremen
Goerschwin Fey , University of Bremen
Rolf Drechsler , University of Bremen
pp. 290

Test Synthesis for Datapaths Using Datapath-Controller Functions (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Kazuhiro Suzuki , Nara Institute of Science and Technology
Hiroyuki Okamoto , Nara Institute of Science and Technology
Michiko Inoue , Nara Institute of Science and Technology
pp. 294

Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis (Abstract)

Shan Gu , Tsinghua University
Hideo Fujiwara , Nara Institute of Science and Technology
Dong Xiang , Tsinghua University
pp. 300
Session 6B: Test Scheduling

null (PDF)

pp. null

Optimal System-on-Chip Test Scheduling (Abstract)

Erik Larsson , Link?pings Universitet and Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 306

SOC Test Time Minimization Under Multiple Constraints (Abstract)

Zebo Peng , Link?pings Universitet
Julien Pouget , Link?pings Universitet
Erik Larsson , Link?pings Universitet
pp. 312

Test Time Minimization for Hybrid BIST of Core-Based Systems (Abstract)

Gert Jervan , Link?ping University
Maksim Jenihhin , Tallinn Technical University
Raimund Ubar , Tallinn Technical University
Zebo Peng , Link?ping University
Petru Eles , Link?ping University
pp. 318
Session 6C: Measurement

null (PDF)

pp. null

On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization (Abstract)

Tian Xia , University of Vermont
Jien-Chung Lo , University of Rhode Island
pp. 326

An On-Chip Jitter Measurement Circuit for the PLL (Abstract)

Chin-Cheng Tsai , National Chaio Tung University
Chung-Len Lee , National Chaio Tung University
pp. 332

A Low-Cost Jitter Measurement Technique for BIST Applications (Abstract)

Jui-Jer Huang , National Taiwan University
Jiun-Lang Huang , National Taiwan University
pp. 336

Measurement-Based Modeling with Adaptive Sampling (Abstract)

Gaogang Xie , Chinese Academy of Sciences
Jianhua Yang , Chinese Academy of Sciences
Mingtian Zhou , University of Electric Science and Technology of China
Zhongcheng Li , Chinese Academy of Sciences
Junfeng Wang , University of Electric Science and Technology of China
pp. 340
Session 7A: Test Economics

null (PDF)

pp. null

Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing (Abstract)

Baosheng Wang , University of British Columbia
Yong B. Cho , Konkuk University
Andr? Ivanov , University of British Columbia
Sassan Tabatabaei , Vector 12 Corporation
pp. 348

Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method (Abstract)

Michael R. Grimaila , Texas A&M University
Weiping Shi , Texas A&M University
Yuxin Tian , Texas A&M University
M. Ray Mercer , Texas A&M University
pp. 354
Session 7B: Memory Testing 3

null (PDF)

pp. null

A Processor-Based Built-In Self-Repair Design for Embedded Memories (Abstract)

Rei-Fu Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Chin-Lung Su , National Tsing Hua University
pp. 366

March SL: A Test For All Static Linked Memory Faults (Abstract)

Said Hamdioui , Delft University of Technology and Intel Corporation
Mike Rodgers , Intel Corporation
Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 372

Testing Delay Faults in Embedded CAMs (Abstract)

Wu-Tung Cheng , Mentor Graphics Corporation
Xiaogang Du , University of Iowa
Sudhakar M. Reddy , University of Iowa
Joseph Rayhawk , Mentor Graphics Corporation
pp. 378

Stress Test for Disturb Faults in Non-Volatile Memories (Abstract)

Mohammad Gh. Mohammad , Kuwait University
Kewal K. Saluja , University of Wisconsin-Madison
pp. 384
Session 7C: Current Test

null (PDF)

pp. null

A BIST Circuit for I<sub>DDQ</sub> Tests (Abstract)

Kozo Kinoshita , Osaka Gakuin University
Yukiya Miura , Tokyo Metropolitan University
Takeomi Tamesada , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
Teppei Takeda , University of Tokushima
Masaki Hashizume , University of Tokushima
pp. 390

At-Speed Current Testing (Abstract)

Yinghua Min , Hunan University
Xiaoyan Niu , Hunan University
Jishun Kuang , Hunan University
pp. 396

I<sub>DDT</sub> ATPG Based on Ambiguous Delay Assignments (Abstract)

Yu Wang , Hunan University
Changnian Zhang , University of Regina
Jishun Kuang , Hunan University
Xiaofen Wei , Hunan University
pp. 400

Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test (Abstract)

Hiroyuki Michinishi , Okayama University of Science
Tokumi Yokohira , Okayama University
Takuji Okamoto , Okayama University of Science
Toshifumi Kobayashi , Mitsubishi Electric Co.
Tsutomu Hondo , Sharp Takaya Electronics Industry Co.,Ltd.
pp. 406
Session 8A: SOC DFT

null (PDF)

pp. null

A DFT Selection Method for Reducing Test Application Time of System-on-Chips (Abstract)

Toshinori Hosokawa , Semiconductor Technology Academic Research Center
Hiroshi Date , Semiconductor Technology Academic Research Center
Michiaki Muraoka , Semiconductor Technology Academic Research Center
Hideo Fujiwara , Nara Institute of Science and Technology
Masahide Miyazaki , Semiconductor Technology Academic Research Center
pp. 412

Sharing BIST with Multiple Cores for System-on-a-Chip (Abstract)

Huaguo Liang , Hefei University of Technology
Cuiyun Jiang , Hefei University of Technology
pp. 418

Designing Multiple Scan Chains for Systems-on-Chip (Abstract)

Md. Saffat Quasem , University of Southern California
Sandeep Gupta , University of Southern California
pp. 424
Session 8B: Test Compaction 2

null (PDF)

pp. null

Test Data Volume Reduction by Test Data Realignment (Abstract)

Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 434

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction (Abstract)

Huawei Li , Chinese Academy of Science
Yinhe Han , Chinese Academy of Science
Anshuman Chandra , Synopsys, Inc.
Xiaowei Li , Chinese Academy of Science
Yongjun Xu , Chinese Academy of Science
pp. 440

Test Response Compression Based on Huffman Coding (Abstract)

Tomoo Inoue , Hiroshima City University
Hideyuki Ichihara , Hiroshima City University
Toshihiro Ohara , Hiroshima City University
Michihiro Shintani , Hiroshima City University
pp. 446
Session 8C: Functional Testing/Reliability

null (PDF)

pp. null

Probability Model for Faults in Large-Scale Multicomputer Systems (Abstract)

Guojun Wang , Central South University
Songqiao Chen , Central South University
Gaocai Wang , Central South University
Jianer Chen , Central South University
pp. 452

Design Retargetable Platform System for Microprocessor Functional Test (Abstract)

Wennan Feng , Peking University
Lijiu Ji , Peking University
Anping Jiang , Peking University
Song Jia , Peking University
Ling Liu , Peking University
pp. 458

Assessing Software Implemented Fault Detection and Fault Tolerance Mechanisms (Abstract)

J. Sosnowski , Warsaw University of Technology
P. Gawkowski , Warsaw University of Technology
pp. 462

Briefing a New Approach to Improve the EMI Immunity of DSP Systems (Abstract)

Daniel Barros Jr. , Catholic University - PUCRS
Rubem D. R. Fagundes , Catholic University - PUCRS
Fabian Vargas , Catholic University - PUCRS
Diogo B. Brum , Catholic University - PUCRS
pp. 468
Session 9A: Formal Verification

null (PDF)

pp. null

Design Error Diagnosis Based on Verification Techniques (Abstract)

Xiaowei Li , Chinese Academy of Sciences
Guanghui Li , Chinese Academy of Sciences and Zhejiang Forestry College
Ming Shao , Chinese Academy of Sciences
pp. 474

SAT-Based Algorithm of Verification for Port Order Fault (Abstract)

Guanghui Li , Chinese Academy of Sciences
Ming Shao , Chinese Academy of Sciences
Xiaowei Li , Chinese Academy of Sciences
pp. 478

Equivalence Checking Using Independent Cuts (Abstract)

Zhan Xu , Zhejiang University
Xiaolang Yan , Zhejiang University
Haitong Ge , Zhejiang University
Yongjiang Lu , Zhejiang University
pp. 482
Session 9B: Software Testing 3

null (PDF)

pp. null

A Method to Calculate the Reliability of Component-Based Software (Abstract)

Yuan Zhu , Shanghai Normal University
Jianhua Gao , Shanghai Normal University
pp. 488

An Object-Oriented Program Automatic Execute Model and the Research of Algorithm (Abstract)

Yun-Zhan Gong , Armored Force Engineering Institute
Da-Hai Jin , Armored Force Engineering Institute
pp. 492
Poster Session

RTL Concurrent Fault Simulation (PDF)

Li Shen , Chinese Academy of Sciences
pp. 502

Property Classification for Functional Verification Based (PDF)

Hongxi Xue , Tsinghua University
Jinian Bian , Tsinghua University
Weimin Wu , Tsinghua University
Ming Zhu , Tsinghua University
pp. 503

Testability Improvement During High-Level Synthesis (PDF)

Hadi Esmaeilzadeh , University of Tehran
Saeed Safari , Sharif University of Technology
Amir-Hossein Jahangir , Sharif University of Technology
pp. 505

A Test Architecture for System-on-a-Chip (PDF)

Jin-xiang Wang , Harbin Institute of Technology
Ming-yan Yu , Harbin Institute of Technology
Yi-zheng Ye , Harbin Institute of Technology
Yong-sheng Wang , Harbin Institute of Technology
Li-yi Xiao , Harbin Institute of Technology
pp. 506

Test Pattern Length Required to Reach the Desired Fault Coverage (PDF)

Junichi Hirase , Matsushita Electric Industrial Co., Ltd.
pp. 508

Study on the Cost/Benefit/Optimization of Software Safety Test (PDF)

Zhu Xu , Tongji University
Meng Li , Tongji University
pp. 510
Author Index

Author Index (PDF)

pp. 511
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