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Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). (2002)
Guam, USA
Nov. 18, 2002 to Nov. 20, 2002
ISSN: 1081-7735
ISBN: 0-7695-1825-7
TABLE OF CONTENTS
Section 1A: Test Generation

On Generating High Quality Tests for Transition Faults (Abstract)

Yun Shao , University of Iowa
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 1

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests (Abstract)

Ilia Polian , Albert-Ludwigs University
Irith Pomeranz , Purdue University
Bernd Becker , Albert-Ludwigs University
pp. 9

Maximum Distance Testing (Abstract)

Shiyi Xu , Shanghai University
Jianwen Chen , Shanghai University
pp. 15
Section 1B: On-Line Testing

High Precision Result Evaluation of VLSI (Abstract)

Junichi Hirase , Matsushita Electric Industrial Co., Ltd.
pp. 21

A Totally Self-Checking Dynamic Asynchronous Datapath (Abstract)

Jing-ling Yang , The University of Hong Kong
Chiu-sing Choy , The Chinese University of Hong Kong
Cheong-fat Chan , The Chinese University of Hong Kong
Kong-pong Pun , The Chinese University of Hong Kong
pp. 27
Session 1C: Analog and Mixed Signal Testing

Test Limitations of Parametric Faults in Analog Circuits (Abstract)

Jacob Savir , New Jersey Institute of Technology
Zhen Guo , New Jersey Institute of Technology
pp. 39

Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices (Abstract)

Masahiro Ishida , Advantest Laboratories, Ltd.
Takahiro J. Yamaguchi , Advantest Laboratories, Ltd.
Mana Sona , University of Washington
Hirobumi Musha , Advantest Corporation
pp. 45

On-chip Analog Response Extraction with 1-Bit &Egr; - Δ Modulators (Abstract)

Hao-Chiao Hong , National Tsing Hua University
Jiun-Lang Huang , National Taiwan University
Kwang-Ting Cheng , University of California, Santa Barbara
Cheng-Wen Wu , National Tsing Hua University
pp. 49
Session 2A: Test Set Compaction

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique (Abstract)

Toshinori Hosokawa , Semiconductor Technology Academic Research Center (STARC)
Hiroshi Date , Semiconductor Technology Academic Research Center (STARC)
Michiaki Muraoka , Semiconductor Technology Academic Research Center (STARC)
pp. 55

Test Data Compression Using Don?t-Care Identification and Statistical Encoding (Abstract)

Seiji Kajihara , Kyushu Institute of Technology
Kenjiro Taniguchi , Kyushu Institute of Technology
Kohei Miyase , Kyushu Institute of Technology
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 67
Session 2B: Design for Testability

Design for Two-Pattern Testability of Controller-Data Path Circuits (Abstract)

Atlaf Ul Amin , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 73

MD-SCAN Method for Low Power Scan Testing (Abstract)

Takaki Yoshida , Matsushita Electric Industrial Co., Ltd.
Masafumi Watari , Matsushita Electric Industrial Co., Ltd.
pp. 80

Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis (Abstract)

Dong Xiang , Tsinghua University
Shan Gu , Tsinghua University
Hideo Fujiwara , Nara Institute of Science and Technology.
pp. 86
Session 2C: Memory Testing 1

Specification and Design of a New Memory Fault Simulator (Abstract)

A. Benso , Politecnico di Torino
S. Di Carlo , Politecnico di Torino
G. Di Natale , Politecnico di Torino
P. Prinetto , Politecnico di Torino
pp. 92

DRAM Specific Approximation of the Faulty Behavior of Cell Defects (Abstract)

Zaid Al-Ars , Delft University of Technology
Ad J. Van de Goor , Delft University of Technology
pp. 98

An Access Timing Measurement Unit of Embedded Memory (Abstract)

Shu-Rong Lee , Nation Tsing-Hua University
Ming-Jun Hsiao , Nation Tsing-Hua University,
Tsin-Yuan Chang , Nation Tsing-Hua University,
pp. 104
Section 3A: Delay Fault Testing

Optimal Seed Generation for Delay Fault Detection BIST (Abstract)

Lihong Tong , Chiba University
Kazuki Suzuki , Chiba University
Hideo Ito , Chiba University
pp. 116
Session 3B: Test Synthesis

A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design (Abstract)

Tomoo Inoue , Hiroshima City University
Tomokazu Miura , Hiroshima City University
Akio Tamura , Hiroshima City University
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 128

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction (Abstract)

Yiorgos Makris , Yale University
Alex Orailogolu , University of California, San Diego
pp. 134
Session 3C: Memory Testing 2

DPSC SRAM Transparent Test Algorithm (Abstract)

Hong-Sik Kim , Yonsei University
Sungho Kang , Yonsei University
pp. 145

Tests for Word-Oriented Content Addressable Memories (Abstract)

Xuemei Zhao , Harbin Institute of Technology
Yizheng Yu , Harbin Institute of Technology
Chunxu Chen , Harbin Institute of Technology
pp. 151

A High Performance IDDQ Testable Cache for Scaled CMOS Technologies (Abstract)

Swarup Bhunia , Purdue University
Hai Li , Purdue University
Kaushik Roy , Purdue University
pp. 157
Session 4A: Crosstalk Fault Testing

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal (Abstract)

Ming Shae Wu , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
Chi Peng Chang , National Chiao Tung University
Jwu E. Chen , Chung Hua University
pp. 170

Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits (Abstract)

Kazuya Shimizu , Osaka University
Noriyoshi Itazaki , Osaka University
Kozo Kinoshita , Ozaka Gakuin University
pp. 176

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits (Abstract)

Marong Phadoongsidhi , University of Wisconsin - Madison
Kim T. Le , University of Canberra
Kewal K. Saluja , University of Wisconsin - Madison
pp. 182
Session 4B: Built-in Self Test 1

Fault Set Partition for Efficient Width Compression (Abstract)

Emil Gizdarski , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 194

A Reseeding Technique for LFSR-Based BIST Applications (Abstract)

Nan-Cheng Li , National Chung-Hsing University
Sying-Jyan Wang , National Chung-Hsing University
pp. 200

A ROMless LFSR Reseeding Scheme for Scan-based BIST (Abstract)

E. Kalligeros , University of Patras
X. Kavousianos , University of Patras
D. Nikolos , University of Patras
pp. 206
Session 4C: Fault-Tolerance

A Fault-Tolerant Architecture for Symmetric Block Ciphers (Abstract)

Min-Kyu Joo , Hongik University
Jin-Hyung Kim , Hongik University
Yoon-Hwa Choi , Hongik University
pp. 212

A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead (Abstract)

Fabian Vargas , Catholic University - PUCRS
Djones Lettnin , Catholic University - PUCRS
Diogo Brum , Catholic University - PUCRS
Dárcio Prestes , Catholic University - PUCRS
pp. 218

Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems (Abstract)

Fabian Vargas , Catholic University - PUCRS
Rubem D.R. Fagundes , Catholic University - PUCRS
Daniel Barros Jr. , Catholic University - PUCRS
pp. 224

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks (Abstract)

Shyue-Kung Lu , Fu Jen Catholic University
Chien-Hung Yeh , Fu Jen Catholic University
pp. 230
Session 5A: Fault Detection and Diagnosis

Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's (Abstract)

Shyue-Kung Lu , Fu Jen Catholic University
Chung-Yang Chen , Fu Jen Catholic University
pp. 236

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints (Abstract)

Keith J. Keller , University of Wisconsin - Madison
Hiroshi Takahashi , Ehime University
Kim T. Le , University of Canberra
Kewal K. Saluja , University of Wisconsin - Madison
Yuzo Takamatsu , Ehime University
pp. 242

Diagnosis Of Byzantine Open-Segment Faults (Abstract)

Shi-Yu Huang , National Tsing-Hua University
pp. 248
Session 5B: Built-in Self Test 2

Robust Space Compaction of Test Responses (Abstract)

Alexej Dmitriev , University of Potsdam
Michael Gössel , University of Potsdam
Krishnendu Chakrabarty , Duke University
pp. 254

An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS) (Abstract)

Niloy Ganguly , IISWBM
Anindyasundar Nandi , Bengal Engineering College
Sukanta Das , Bengal Engineering College
Biplab K. Sikdar , Bengal Engineering College
P. Pal Chaudhuri , Bengal Engineering College
pp. 260

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters (Abstract)

Sheng-Hung Hsieh , National Tsing Hua University
Ming-Jun Hsiao , National Tsing Hua University
Tsin-Yuan Chang , National Tsing Hua University
pp. 266
Session 5C: Software Testing

An Analytic Software Testability Model (Abstract)

Jin-Cherng Lin , Tatung University
Szu-Wen Lin , Tatung University
pp. 278
Session 6: Special Session - Test Strategies and Case Studies for SoC in Industries

A Test Point Insertion Method to Reduce the Number of Test Patterns (Abstract)

Masayoshi Yoshimura , Matsushita Electric Industrial Co., Ltd.
Toshinori Hosokawa , Semiconductor Technology Academic Research Center (STARC)
Mitsuyasu Ohta , Matsushita Electric Industrial Co., Ltd.
pp. 298

A SoC Test Strategy Based on a Non-Scan DFT Method (Abstract)

Hiroshi Date , Semiconductor Technology Academic Research Center (STARC)
Toshinori Hosokawa , Semiconductor Technology Academic Research Center (STARC)
Michiaki Muraoka , Semiconductor Technology Academic Research Center (STARC)
pp. 305

Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips (Abstract)

Kazuhiko Iijima , LogicVision, Inc.
Armagan Akar , LogicVision, Inc.
Charlie McDonald , LogicVision, Inc.
Dwayne Burek , LogicVision, Inc.
pp. 311

Manufacturing Test of SoCs (Abstract)

Rohit Kapur , Synopsys Inc.
T.W. Williams , Synopsys Inc.
pp. 317

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs (Abstract)

Vikram Iyengar , IBM Microelectronics
Krishnendu Chakrabarty , Duke University
Erik Jan Marinissen , Philips Research Laboratories
pp. 320
Session 7A: Test Power Reduction

Test Power Optimization Techniques for CMOS Circuits (Abstract)

Zuying Lo , TsingHua University
Xiaowei Li , Chinese Academy of Sciences
Huawei Li , Chinese Academy of Sciences
Shiyuan Yang , TsingHua University
Yinghua Min , Chinese Academy of Sciences
pp. 332
Session 7B: System-on-Chip Testing 1

A Simple Wrapped Core Linking Module for SoC Test Access (Abstract)

Jaehoon Song , Hanyang University
Sungju Park , Hanyang University
pp. 344

Testing System-On-Chip by Summations of Cores? Test Output Voltages (Abstract)

K.Y. Ko , The Hong Kong Polytechnic University
Mike W.T. Wong , The Hong Kong Polytechnic University
Y.S. Lee , The Hong Kong Polytechnic University
pp. 350

Test Scheduling of BISTed Memory Cores for SOC (Abstract)

Chih-Wea Wang , National Tsing Hua University
Jing-Reng Huang , National Tsing Hua University
Yen-Fu Lin , National Tsing Hua University
Kuo-Liang Chang , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Chen-Wen Wu , National Tsing Hua University
Youn-Ling Lin , Global UniChip Corp.
pp. 356
Session 7C: Verification and Simulation

Effective Error Diagnosis for RTL Designs in HDLs (Abstract)

Tai-Ying Jiang , National Chiao Tung University
Chien-Nan Jimmy Liu , National Central University
Jing-Yang Jou , National Chiao Tung University
pp. 362

Evolutionary Test Program Induction for Microprocessor Design Verification (Abstract)

Fulvio Corno , Politecnico di Torino
Gianluca Cumani , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
pp. 368

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models (Abstract)

Shahrzad Mirkhani , University of Tehran
Meisam Lavasani , University of Tehran
Zainalabedin Navabi , University of Tehran
pp. 374
Session 8A: Test Systems

Extending EDA Environment From Design to Test (Abstract)

Rochit Rajsuman , Advantest America R&D Center
pp. 386
Session 8B: System-on-Chip Testing 2

Integrated Test Scheduling, Test Parallelization and TAMDesign (Abstract)

Erik Larsson , Nara Institute of Science and Technology; Link?pings Universitet
Klas Arvidsson , Link?pings Universitet
Hideo Fujiwara , Nara Institute of Science and Technology
Zebo Peng , Link?pings Universitet
pp. 397

Core - Clustering Based SOC Test Scheduling Optimization (Abstract)

Yu Huang , Mentor Graphics Corporation
Sudkhkar M. Reddy , University of Iowa
Wu-Tung Cheng , Mentor Graphics Corporation
pp. 405

Test Scheduling and Test Access Architecture Optimization for System-on-Chip (Abstract)

Huan-Shan Hsu , National Tsing Hua University
Jing-Reng Huang , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Chih-Wea Wang , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Youn-Long Lin , Global UniChip Corp.
pp. 411
Session 8C: Current Testing

CMOS Floating Gate Defect Detection Using I <sub>DDQ</sub> Test with DC Power Supply (Abstract)

Hiroyuki Michinishi , Okayama University of Science
Tokumi Yokohira , Okayama University
Takuji Okamoto , Okayama University of Science
Toshifumi Kobayashi , Mitsubishi Electric Co.
Tsutomu Hondo , Sharp Takaya Electronics Industry Co.,Ltd.
pp. 417

Test Time Reduction for I <sub>DDQ</sub> Testing by Arranging Test Vectors (Abstract)

Hiroyuki Yotsuyanagi , University of Tokushima
Masaki Hashizume , University of Tokushima
Takeomi Tamesada , University of Tokushima
pp. 423

Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion (Abstract)

Shambhu Upadhyaya , State University of New York at Buffalo
Jae Min Lee , State University of New York at Buffalo
Padmanabhan Nair , State University of New York at Buffalo
pp. 429

Author Index (PDF)

pp. 435
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