The Community for Technology Leaders
Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02). (2002)
Guam, USA
Nov. 18, 2002 to Nov. 20, 2002
ISSN: 1081-7735
ISBN: 0-7695-1825-7
pp: 92
A. Benso , Politecnico di Torino
S. Di Carlo , Politecnico di Torino
G. Di Natale , Politecnico di Torino
P. Prinetto , Politecnico di Torino
This paper presents a new Fault Simulator architecture for RAM memories. The key features of the proposed tool are: 1) user-definable fault models, test algorithm, and memory architecture; 2) very fast simulation algorithm; 3) ability to compute the coverage of any provided test sequence w.r.t. a user-defined set of fault models, and to eliminate redundant operations; 4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.

P. Prinetto, A. Benso, G. Di Natale and S. Di Carlo, "Specification and Design of a New Memory Fault Simulator," Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).(ATS), Guam, USA, 2002, pp. 92.
93 ms
(Ver 3.3 (11022016))