The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2001)
Kyoto, Japan
Nov. 19, 2001 to Nov. 21, 2001
ISBN: 0-7695-1378-6
TABLE OF CONTENTS

Reviewers (PDF)

pp. xxiii
Plenary Session: Keynote Address

DFT for High-Quality Low Cost Manufacturing Test (Abstract)

Janusz Rajski , Mentor Graphics Corporation, USA
pp. 3
Session 1A: Design for Testability - Chair: Ermenfried Prochaska, Fachhochschule Heilbronn, Germany

Design for Hierarchical Two-Pattern Testability of Data Paths (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Md. Altaf-Ul-Amin , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
pp. 11

A Multiple Phase Partial Scan Design Method (Abstract)

Yi Xu , Tsinghua University
Dong Xiang , Tsinghua University
pp. 17

Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States (Abstract)

Takeomi Tamesada , University of Tokushima
Masaki Hashizume , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
Shinsuke Hata , University of Tokushima
pp. 23
Session 1B: Fault Modeling for Memories - Chair: Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan

Tests for Resistive and Capacitive Defects in Address Decoders (Abstract)

Matthias Klaus , ProMOS Technologies
Ad J. van de Goor , Delft University of Technology
pp. 31

Detecting Unique Faults in Multi-port SRAMs (Abstract)

Said Hamdioui , Intel Corporation and Delft University of Technology
Ad J. van de Goor , Delft University of Technology
Mike Rodgers , Intel Corporation
David Eastwick , Intel Corporation
pp. 37

A Memory Specific Notation for Fault Modeling (Abstract)

Jens Braun , Infineon Technologies AG
Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
Detlev Richter , Infineon Technologies AG
pp. 43
Session 1C: Diagnosis Session - Chair: Shiyi Xu, Shanghai University, China

Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits (Abstract)

Kewal K. Saluja , University of Wisconsin -Madison
Yuzo Takamatsu , Ehime University
Yoshinobu Higami , Ehime University
Marong Phadoongsidhi , University of Wisconsin -Madison
Hiroshi Takahashi , Ehime University
pp. 63
Session 2A: ATPG - Chair: Christian Landrault, LIRMM, France

Test Generation for Double Stuck-at Faults (Abstract)

Yoshinobu Higami , Ehime University
Yuzo Takamatsu , Ehime University
Naoko Takahashi , Ehime University
pp. 71
Session 2B: Embedded Memory Test - Chair: Yervant Zorian, Logic Vision, Inc., USA

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip (Abstract)

Jen-Chieh Yeh , National Tsing Hua University
Kuo-Liang Cheng , National Tsing Hua University
Chia-Ming Hsueh , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Jing-Reng Huang , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
pp. 91

A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis (Abstract)

D. Appello , STMicroelectronics
F. Corno , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Giovinetto , Politecnico di Torino
pp. 97

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters (Abstract)

Shyh-Horng Lin , SynTest Technologies,Inc.
Cheng-Wen Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Hsin-Po Wang , SynTest Technologies,Inc.
Chih-Wea Wang , National Tsing Hua University
Chi-Feng Wu , National Tsing Hua University
Ruey-Shing Tzeng , National Tsing Hua University
Shi-Yu Huang , National Tsing Hua University
pp. 103
Session 2C: IDDQ and Diagnosis Test - Chair: Hiroshi Yokoyama, Akita University, Japan

IDDQ Sensing Technique for High Speed IDDQ Testing (Abstract)

Masaki Hashizume , The University of Tokushima
Kozo Kinoshita , Osaka Gakuin University
Yukiya Miura , Tokyo Metropolitan University
Hiroyuki Yotsuyanagi , The University of Tokushima
Masahiro Ichimiya , The University of Tokushima
Teppei Takeda , The University of Tokushima
pp. 111

CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application (Abstract)

Masahiro Ichimiya , University of Tokushima
Takeomi Tamesada , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
Masaki Hashizume , University of Tokushima
pp. 117

An Approach to Improve the Resolution of Defect-Based Diagnosis (Abstract)

Toshio Ikeda , Hitachi, Ltd.
Yasuo Sato , Hitachi, Ltd.
Hiroki Yamanaka , Hitachi, Ltd.
Iwao Yamazaki , Hitachi, Ltd.
Masahiro Takakura , Hitachi Engineering Co., Ltd.
pp. 123
Session 3A: Test Compaction - Chair: Toshinori Hosokawa, Semiconductor Technology Academic Research Center, Japan

A Method of Static Compaction of Test Stimuli (Abstract)

Kwame Osei Boateng , Fujitsu Labs. Ltd.
Hideaki Konishi , Fujitsu Co.
Tsuneo Nakata , Fujitsu Labs. Ltd.
pp. 137

Dynamic Test Compression Using Statistical Coding (Abstract)

Tomoo Inoue , Hiroshima City University
Atsuhiro Ogawa , Hiroshima City University
Akio Tamura , Hiroshima City University
Hideyuki Ichihara , Hiroshima City University
pp. 143
Session 3B: Pattern Generation for Memory Test - Chair: Tetsuo Tada, Mitsubishi Electric Corporation, Japan

Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing (Abstract)

Mill-Jer Wang , Vanguard International Semiconductor Corporation
R.-L. Jiang , Vanguard International Semiconductor Corporation
Chih-Hu Wang , Chung-Hua University
J.-W. Hsia , Vanguard International Semiconductor Corporation
Jwu E. Chen , Chung-Hua University
pp. 151

Memory Read Faults: Taxonomy and Automatic Test Generation (Abstract)

Paolo Prinetto , Politecnico di Torino
Giorgio Di Natale , Politecnico di Torino
Alfredo Benso , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
pp. 157

Simulation and Development of Short Transparent Tests for RAM (Abstract)

S. Henderson , Massey University
P. Knoppers , Delft University of Technology
S. Demidenko , Massey University
A. van de Goor , Delft University of Technology
pp. 164
Session 3C: Virtual Tester and Beam Testing - Chair: Koji Nakamae, Osaka University, Japan

EB-Testing-Pad Method and Its Evaluation by Actual Devices (Abstract)

Takako Ishihara , NTT Electronics Co. and NTT Telecommunications Energy Laboratories
Norio Kuji , NTT Electronics Co. and NTT Telecommunications Energy Laboratories
pp. 179

Benefits of Phase Interference Detection to IC Waveform Probing (Abstract)

Chris Shaw , Schlumberger Probe Systems
William K. Lo , Schlumberger Probe Systems
Jeffrey A. Block , Schlumberger SABER
pp. 185
Session 4A: SoC Test Access Mechanism - Chair: Hiroshi Date, ABEL Systems Inc., Japan
Session 4B: RTL ATPG - Chair: Jacob A. Abraham, University of Texas at Austin, USA

An RT-Level ATPG Based on Clustering of Circuit States (Abstract)

Zhongcheng Li , Chinese Academy of Sciences
Huawei Li , Chinese Academy of Sciences
Yinghua Min , Chinese Academy of Sciences
pp. 213

An Approach to RTL Fault Extraction and Test Generation (Abstract)

Zhigang Yin , Chinese Academy of Sciences
Yinghua Min , Chinese Academy of Sciences
Xiaowei Li , Chinese Academy of Sciences
pp. 219

Effective Techniques for High-Level ATPG (Abstract)

Gianluca Cumani , Politecnico di Torino
Matteo Sonza Reorda , Politecnico di Torino
Fulvio Corno , Politecnico di Torino
Giovanni Squillero , Politecnico di Torino
pp. 225
Session 4C: Delay Test - Chair: Jacob Savir, New Jersey Institute of Technology, USA

An Efficient Method to Identify Untestable Path Delay Faults (Abstract)

Yun Shao , University of Iowa
Seiji Kajihara , Kyushu Institute of Technology
Irith Pomeranz , Purdue University
Sudhakar M. Reddy , University of Iowa
pp. 233

SpeedGrade: An RTL Path Delay Fault Simulator (Abstract)

Rathish Jayabharathi , Intel Corporation
Kee Sup Kim , Intel Corporation
Craig Carstens , Intel Corporation
pp. 239

Test Generation for Multiple-Threshold Gate-Delay Fault Model (Abstract)

Michinobu Nakao , Hitachi Ltd.
Yoshikazu Kiyoshige , Hitachi Ltd.
Takaharu Nagumo , Hitachi Ltd.
Yasu Sato , Hitachi Ltd.
Kazumi Hatayama , Hitachi Ltd.
pp. 244
Session 5A: SoC Test Scheduling - Chair: Prab Varma, Veritable Inc., USA

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores (Abstract)

Y. Bonhomme , Universit? Montpellier II /CNRS
P. Girard , Universit? Montpellier II /CNRS
L. Guiller , Universit? Montpellier II /CNRS
C. Landrault , Universit? Montpellier II /CNRS
S. Pravossoudovitch , Universit? Montpellier II /CNRS
pp. 253

Test Scheduling and Scan-Chain Division under Power Constraint (Abstract)

Zebo Peng , Link?pings University
Erik Larsson , Link?pings University
pp. 259

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D (Abstract)

Yu Huang , University of Iowa
Chien-Chung Tsai , Mentor Graphics Corporation
Wu-Tung Cheng , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa
Nilanjan Mukherjee , Mentor Graphics Corporation
Omer Samman , Mentor Graphics Corporation
Yahya Zaidan , Mentor Graphics Corporation
pp. 265
Session 5B: FSM Test - Chair: Hiroshi Takahashi, Ehime University, Japan

A Unified Scheme for Designing Testable State Machines (Abstract)

P. K. Lala , University of Arkansas
A. Walker , North Carolina A&T State University
pp. 273

Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines (Abstract)

Samrat Goswami , Indian Institute of Technology at Kharagpur
Anupam Chanda , Indian Institute of Technology at Kharagpur
D. Roy Choudhury , Indian Institute of Technology at Kharagpur
pp. 279

Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis (Abstract)

Samir Roy , Kalyani Government Engineering College
Debesh K Das , Jadavpur University
Biplab K Sikdar , Bengal Engineering College
pp. 285
Session 5C: Online Testing and Fault Injection line - Chair: Masahiro Tsunoyama, Niigata Institute of Technology, Japan

Robust Self Concurrent Test of Linear Digital Systems (Abstract)

Ahmad Abdelhay , TIMA Laboratory
Emmanuel Simeu , TIMA Laboratory
Mohammad A. Naal , TIMA Laboratory
pp. 293

Control-Flow Checking via Regular Expressions (Abstract)

Luca Tagliaferri , Politecnico di Torino
Giorgio Di Natale , Politecnico di Torino
Alfredo Benso , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Stefano Di Carlo , Politecnico di Torino
pp. 299

FPGA-Based Fault Injection for Microprocessor Systems (Abstract)

L. Macchiarulo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
P. Civera , Politecnico di Torino
pp. 304
Session 6A: Advances in BIST - Chair: Kazuhiko Iijima, Logic Vision, Inc., Japan

A BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths (Abstract)

Hiroki Wada , Nara Institute of Science and Technology
Ken-ichi Yamaguchi , Nara Institute of Science and Technology
Toshimitsu Masuzawa , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 313

Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit (Abstract)

Alex Orailoglu , University of California at San Diego
Sobeeh Almukhaizim , University of California at San Diego
Peter Petrov , University of California at San Diego
pp. 319

A SmartBIST Variant with Guaranteed Encoding (Abstract)

Owen Farnsworth , IBM Microelectronics
Carl Barnhart , IBM Microelectronics
Brion Keller , IBM Microelectronics
Bernd Koenemann , IBM Microelectronics
Donald Wheater , IBM Microelectronics
Tom Snethen , IBM Microelectronics
pp. 325
Session 6B: Analog Test - Chair: Yasuo Furukawa, Advantest Corporation, Japan

On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks (Abstract)

Xi Min Zhang , New Jersey Institute of Technology
Yun-Qing Shi , New Jersey Institute of Technology
Jacob Savir , New Jersey Institute of Technology
Zhen Guo , New Jersey Institute of Technology
pp. 338

Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits (Abstract)

Achintya Halder , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 344
Session 6C: Fault Tolerance - Chair: Hideo Ito, Chiba University, Japan

Yield Increase of VLSI after Redundancy-Repairing (Abstract)

Junichi Hirase , Matsushita Electric Industrial Co., Ltd.
pp. 353

An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks (Abstract)

Naotake Kamiura , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
Yasuyuki Taniguchi , Sharp Corporation
Teijiro Isokawa , Himeji Institute of Technology
pp. 359

A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes (Abstract)

M. Gössel , University of Potsdam
E. S. Sogomonya , University of Potsdam
V. Ocheretnij , University of Potsdam
pp. 365
Session 7A: Various Ideas for BIST - Chair: Tokumi Yokohira, Okayama University, Japan

Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? (Abstract)

Alex Orailoglu , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
pp. 373

Hybrid BIST Using Partially Rotational Scan (Abstract)

Takeshi Asakawa , Tokyo Metropolitan University
Kenichi Ichino , Tokyo Metropolitan University
Satoshi Fukumoto , Tokyo Metropolitan University
Seiji Kajihara , Kyushu Institute of Technology
Kazuhiko Iwasaki , Tokyo Metropolitan University
pp. 379

Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits (Abstract)

Subha Sankar Chowdhury , Bengal Engineering College
Aniket Karmakar , Bengal Engineering College
Biplab K Sikdar , Bengal Engineering College
P. Pal Chaudhuri , Bengal Engineering College
Niloy Ganguly , IISWBM
pp. 385

A Microcode-Based Memory BIST Implementing Modified March Algorithm (Abstract)

Sungju Park , Hanyang University
Taehyung Kim , Hanyang University
Dongkyu Youn , Hanyang University
pp. 391

Fault Simulation for VHDL Based Test Bench and BIST Evaluation (Abstract)

Zainalabedin Navabi , University of Tehran
Mina Zolfy , University of Tehran
Shahrzad Mirkhani , University of Tehran
Hamed Farshbaf , University of Tehran
pp. 396
Session 7B: Analog/Mixed Signal Test - Chair: Michel Renovell, LIRMM, France

Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models (Abstract)

Biranchinath Sahu , Georgia Institute of Technology
Abhijit Chatterjee , Georgia Institute of Technology
pp. 405

Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology
Alfred V. Gomes , Georgia Institute of Technology
pp. 411

Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft? (Abstract)

A. Lechner , Lancaster University
A. Richardson , Lancaster University
B. Hermes , Philips Semiconductors
pp. 417

An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters (Abstract)

Ming-Jun Hsiao , National Tsing Hua University
Tsin-Yuan Chang , National Tsing Hua University
Jeng-Horng Tsai , National Tsing Hua University
pp. 423
Session 7C: Verification - Chair: Kiyoharu Hamaguchi, Osaka University, Japan
Poster Session 1: DFT Application to Real Chips

A Practical Logic BIST for ASIC Designs (PDF)

M. Kawashima , Hitachi, Ltd.
Y. Sato , Hitachi, Ltd.
K. Tsutsumida , Hitachi, Ltd.
M. Sato , Hitachi, Ltd.
T. Ikeya , Hitachi, Ltd.
pp. 457

Tx7901 Dft (PDF)

Tetsuo Kamada , Toshiba Corporation Semiconductor Company
pp. 458

An Application of Partial Scan Techniques to a High-End System LSI Design (PDF)

Takashi Kimura , NEC Software Hokuriku, LTD.
Yoshihiro Konno , NEC Corporation
Koji Saga , NEC Corporation
Toshinobu Ono , NEC Corporation
Akira Kozawa , NEC Software Hokuriku, LTD.
pp. 459

Built-out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs (PDF)

Shinji Yamada , Mitsubishi Electric Corporation
Teruhiko Funakura , Mitsubishi Electric Corporation
Hisayoshi Hanai , Mitsubishi Electric Corporation
Eisaku Yamashita , Mitsubishi Electric Corporation
Hisaya Mori , Mitsubishi Electric Corporation
pp. 460

High-Speed Interface Testing (PDF)

M. Suzuki , Fujitsu Ltd.
K. Nakamura , Fujitsu Ltd.
R. Shimizu , Fujitsu Ltd.
N. Naka , Fujitsu Ltd.
pp. 461

A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip (PDF)

Hiroshi Kadota , Matsushita Electric Industrial Co,. Ltd.
Mitsuyasu Ohta , Matsushita Electric Industrial Co,. Ltd.
Takashi Taniguchi , Matsushita Electric Industrial Co,. Ltd.
Tetsuji Kishi , Matsushita Electric Industrial Co,. Ltd.
pp. 462

A Flexible Logic BIST Scheme and Its Application to SoC Designs (PDF)

Xiaoqing Wen , SynTest Technologies, Inc.
Hsin-Po Wang , SynTest Technologies, Inc.
pp. 463
Poster Session 2: Practical Ideas from Universities

Non-exhaustive Parity Testing (PDF)

Shiyi Xu , Shanghai University
pp. 468

A Low-Power LFSR Architecture (PDF)

Kuen-Jong Lee , National Cheng Kung University
Tsung-Chu Huang , National Cheng Kung University
pp. 470

Author Index (PDF)

pp. 471
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