The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2001)
Nov. 19, 2001 to Nov. 21, 2001
ISBN: 0-7695-1233-x
TABLE OF CONTENTS

Preface (PDF)

pp. x
ATS 1992

An Approach to Design-for-Testability for Memory Embedding Logic LSIs (Abstract)

Kazumi Hatayama , Hitachi, Ltd.
Satoshi Michishita , Hitachi, Ltd.
Terumine Hayashi , Hitachi, Ltd.
Hiroyuki Satoh , Hitachi, Ltd.
Masahiro Takakura , Hitachi, Ltd.
Takeshi Suzuki , Hitachi, Ltd.
pp. 3

Reduction of Dynamic Memory Usage in Concurrent Fault Simulation for Synchronous Sequential Circuits (Abstract)

Kewal K. Saluja , University of Wisconsin-Madison
Kyuchull Kim , University of Wisconsin-Madison
pp. 27
ATS 1993

A Two-Phase Fault Simulation Scheme for Sequential Circuits (Abstract)

Wen Ching Wu , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
pp. 41

GID-Testable Two-Dimensional Sequential Arrays for Self-Testing (Abstract)

Wei Kang Huang , Fudan University
Mi Lu , Texas A&M University
F. Lombardi , Texas A&M University
pp. 47

A Global BIST Methodology (Abstract)

P. Varma , Crosscheck Technology
T. Gheewala , Crosscheck Technology
H. Sucar , Crosscheck Technology
pp. 52
ATS 1994

Design of Random Pattern Testable Floating Point Adders (Abstract)

J. Rajski , McGill University
J. Tyszer , McGill University
pp. 73

Testability Considerations in Technology Mapping (Abstract)

Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , University of Iowa
pp. 79

Analysis and Improvement of Testability Measure Approximation Algorithms (Abstract)

Jawahar Jain , Fujitsu Laboratories of America
James Bitner , The University of Texas at Austin
Donald S. Fussell , The University of Texas at Austin
Jacob A. Abraham , The University of Texas at Austin
pp. 85
ATS 1995

DC Control and Observation Structures for Analog Circuits (Abstract)

Yeong-Ruey Shieh , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 112

Universal Test Complexity of Field-Programmable Gate Arrays (Abstract)

Tomoo Inoue , Nara Institute of Science and Technology
Takuji Okamoto , Okayama University
Hiroyuki Michinishi , Okayama University
Hideo Fujiwara , Nara Institute of Science and Technology
Tokumi Yokohira , Okayama University
pp. 119

A Design-for-Test Technique for Multi-stage Analog Circuits (Abstract)

F. Azaïs , Universit? de Montpellier
Y. Bertrand , Universit? de Montpellier
M. Renovell , Universit? de Montpellier
pp. 126

Fanout Fault Analysis for Digital Logic Circuits (Abstract)

Wen Zen Shen , National Chiao Tung University
Beyin Chen , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
Jwu E Chen , Chung-Hua Polytechnic Institute
pp. 133

Theory and Applications of Cellular Automata for Synthesis of Easily Testable Combinational Logic (Abstract)

S Nandi , Indian Institute of Technology
P. Pal Chaudhuri , Indian Institute of Technology
pp. 140

Low Power Design and Its Testability (Abstract)

Hiroaki Ueda , Osaka University
Kozo Kinoshita , Osaka University
pp. 148
ATS 1996

Redundancy Identification Using Transitive Closure (Abstract)

Vishwani D. Agrawal , Lucent Technologies
Qing Lin , Sun Microsystems
Michael L. Bushnell , Rutgers University
pp. 157

A Consistent Scan Design System for Large-Scale ASICs (Abstract)

Tatsushige Bitoh , NEC Corporation
Kazushi Nakamura , NEC Corporation
Koji Saga , NEC Corporation
Seiken Yano , NEC Corporation
Yoshihiro Konno , NEC Corporation
pp. 163

Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults (Abstract)

Kuen- Jong Lee , National Cheng-Kung University
Tsung-Chu Huang , National Cheng-Kung University
Jing- Jou Tang , Nan-Tai Institute of Technology
Cheng-Liang Tsai , National Cheng-Kung University
pp. 169

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique (Abstract)

Seiji Kajihara , Kyusyu Institute of Technology
Yoshinobu Higami , Osaka University
Kozo Kinoshita , Osaka University
pp. 175

An Efficient Compact Test Generator for I<sub>DDQ</sub> Testing (Abstract)

Kwang-Ting Cheng , University of California
Hisashi Kondo , Kawasaki Steel Corp.
pp. 181
ATS 1997

On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs (Abstract)

Satoshi Miyazaki , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
Tomoo Inoue , Nara Institute of Science and Technology
pp. 195

Testing for the Programming Circuit of LUT-Based FPGAs (Abstract)

T. Yokohira , Okayama University
T. Okamoto , Okayama University
T. Inoue , Nara Institute of Science and Technology
H. Fujiwara , Nara Institute of Science and Technology
H. Michinishi , Okayama University
pp. 201

Test Length for Random Testing of Sequential Machines Application to RAMs (Abstract)

René DAVID , Laboratoire d?Automatique de Grenoble
pp. 207

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits (Abstract)

M. Sonza Reorda , Politecnico di Torino
P. Prinetto , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
G. Squillero , Politecnico di Torino
F. Corno , Politecnico di Torino
pp. 213

On Chip Weighted Random Patterns (Abstract)

Jacob Savir , New Jersey Institute of Technology
pp. 219
ATS 1998

March LA: A Test for All Linked Memory Faults (Abstract)

A.J. van de Goor , Delft University of Technology
G.N. Gaydadjiev , Delft University of Technology
V.N. Yarmolik , Belarusian State Univ. of Informatics and Radioelectroniks,
V.G. Mikitjuk , Belarusian State Univ. of Informatics and Radioelectroniks
pp. 240

Test Cycle Count Reduction in a Parallel Scan BIST Environment (Abstract)

Prab Varma , Duet Technologies Inc.
Bechir Ayari , Duet Technologies Inc.
pp. 248

A Ring Architecture Strategy for BIST Test Pattern Generation (Abstract)

C. Landrault , Laboratoire d?informatique de Robotique et de Microe?lectrortique de Montpellier
O. Gascuel , Laboratoire d?informatique de Robotique et de Microe?lectrortique de Montpellierr
C. Fagot , Laboratoire d?informatique de Robotique et de Microe?lectrortique de Montpellier
P. Girard , Laboratoire d?informatique de Robotique et de Microe?lectrortique de Montpellier
pp. 269
ATS 1999

High Resolution CD-SEM System (Abstract)

Hideo Todokoro , Hitachi, Ltd.
Yoichi Ose , Hitachi, Ltd.
Makoto Ezumi , Hitachi, Ltd.
pp. 277

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption (Abstract)

C. Landrault , Universit? Montpellier II / CNRS
S. Pravossoudovitch , Universit? Montpellier II / CNRS
L. Guiller , Universit? Montpellier II / CNRS
P. Girard , Universit? Montpellier II / CNRS
pp. 296

New DFT Techniques of Non-scan Sequential Circuits with Complete Fault Efficiency (Abstract)

Debesh Kumar Das , Jadavpur University
Satoshi Ohtake , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 302
ATS 2000

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results (Abstract)

Wei-Yu Chen , University of Southern California
Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 311

A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption (Abstract)

Emil Gizdarski , Nara Institute of Sience and Technology; University of Rousse
Hideo Fujiwara , Nara Institute of Sience and Technology
Michiko Inoue , Nara Institute of Sience and Technology
pp. 317

A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation (Abstract)

Liang-Chi Chen , University of Southern California
Melvin A. Breuer , University of Southern California
Sandeep K. Gupta , University of Southern California
pp. 329

Accelerated Test Pattern Generators for Mixed-Mode BIST Environments (Abstract)

Kuen-Jong Lee , National Cheng Kung University
Wei-Lun Wang , National Cheng Kung University
pp. 335
ATS 2001

Short Circuit Faults in State-of-the-Art ADCs -- Are They Hard or Soft? (Abstract)

A. Richardson , Lancaster University
B. Hermes , Philips Semiconductors
A. Lechner , Lancaster University
pp. 343

EB-Testing-Pad Method and Its Evaluation by Actual Devices (Abstract)

Norio Kuji , NTT Electronics Co. and NTT Telecommunications Energy Laboratories
Takako Ishihara , NTT Electronics Co. and NTT Telecommunications Energy Laboratories
pp. 349

Robust Self Concurrent Test of Linear Digital Systems (Abstract)

Mohammad A. NAAL , TIMA Laboratory
Emmanuel SIMEU , TIMA Laboratory
Ahmad ABDELHAY , TIMA Laboratory
pp. 355

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design (Abstract)

Yu Huang , University of Iowa
Omer Samman , Mentor Graphics Corporation
Yahya Zaidan , Mentor Graphics Corporation
Chien-Chung Tsai , Mentor Graphics Corporation
Nilanjan Mukherjee , Mentor Graphics Corporation
Sudhakar M. Reddy , University of Iowa
Wu-Tung Cheng , Mentor Graphics Corporation
pp. 361

Design for Hierarchical Two-Pattern Testability of Data Paths (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
Md. Altaf-Ul-Amin , Nara Institute of Science and Technology
pp. 367

Author Index (PDF)

pp. 373
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