The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (2000)
Taipei, Taiwan
Dec. 4, 2000 to Dec. 6, 2000
ISSN: 1081-7735
ISBN: 0-7695-0887-1
TABLE OF CONTENTS

Program Committee (PDF)

pp. xxii

Reviewers (PDF)

pp. xxiii
Keynote Address I
Keynote Address II
Industry Session I: CAD Tools on Testing, Chair: Jing-Yang Jou, National Chiao Tung University, Taiwan

DFT and BIST techniques for the future (Abstract)

Hsin-Po Wang , SynTest Technols. Inc., Taiwan
J. Turino , SynTest Technols. Inc., Taiwan
pp. 6

DFT closure (Abstract)

T.W. Williams , Synopsis Inc., Mountain View, CA, USA
D. Hsu , Synopsis Inc., Mountain View, CA, USA
F. Hayat , Synopsis Inc., Mountain View, CA, USA
R. Kapur , Synopsis Inc., Mountain View, CA, USA
pp. 8

Current status and future trend on CAD tools for VLSI testing (Abstract)

Wu-Tung Cheng , Mentor Graphics Corp., Wilsonville, OR, USA
pp. 10
Industry Session II: Taiwan Test Industry: Value Added Testing in the New Millennium, Chair: Chung-Len Lee, National Chiao Tung University, Taiwan

(PDF)

pp. 13
Panel I
Panel II
Session A1: Analog & Mixed Signal Test I, Chair: Kiyoshi Furuya, Chuo University, Japan

Test generation for fault isolation in analog circuits using behavioral models (Abstract)

S. Cherubal , Georgia Inst. of Technol., Atlanta, GA, USA
A. Chatterjee , Georgia Inst. of Technol., Atlanta, GA, USA
pp. 19

Fault diagnosis for linear analog circuits (Abstract)

Jwu-E Chen , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung-Len Lee , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chau-Chin Su , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jun-Weir Lin , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 25

Testing mixed-signal cores: practical oscillation-based test in an analog macrocell (Abstract)

D. Vazquez , Inst. de Microelectron., Seville Univ., Spain
E. Peralias , Inst. de Microelectron., Seville Univ., Spain
J.L. Huertas , Inst. de Microelectron., Seville Univ., Spain
G. Huertas , Inst. de Microelectron., Seville Univ., Spain
A. Rueda , Inst. de Microelectron., Seville Univ., Spain
pp. 31

New built-in self-test technique based on addition/subtraction of selected node voltages (Abstract)

M.W.T. Wong , Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
K.Y. Ko , Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
pp. 39
Session A2: Memory Built-in Self-Test and Self-Diagnosis, Chair: Ad J. van de Goor, Delft University of Technology, The Netherlands

A built-in self-test and self-diagnosis scheme for embedded SRAM (Abstract)

Jin-Fu Li , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Hsiao-Ping Lin , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Wea Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chi-Feng Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
K. Chiu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
T. Teng , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 45

An FPGA-based re-configurable functional tester for memory chips (Abstract)

K.T. Cheng , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
J.R. Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
C.W. Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
C.K. Ong , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 51

BIST TPG for SRAM cluster interconnect testing at board level (Abstract)

S.K. Gupta , Lucent Technols., Princeton, NJ, USA
Chen-Huan Chiang , Lucent Technols., Princeton, NJ, USA
pp. 58

Efficient built-in self-test algorithm for memory (Abstract)

Sying-Jyan Wang , Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
Chen-Jung Wei , Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
pp. 66
Session B1: Analog & Mixed Signal Test II, Chair: M.D. Shieh, National Yunlin Technical University, Taiwan

Optimal test-set generation for parametric fault detection in switched capacitor filters (Abstract)

Wooyoung Choi , Minnesota Univ., Minneapolis, MN, USA
R. Harjani , Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota , Minnesota Univ., Minneapolis, MN, USA
pp. 72

TI-BIST: a temperature independent analog BIST for switched-capacitor filters (Abstract)

M. Lubaszewski , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
Y. Bertrand , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
M. Renovell , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
F. Azais , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
E. Cota , Dept. de Engenharia Eletrika, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 78

Analog circuit equivalent faults in the D.C. domain (Abstract)

Y.S. Lee , Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
M. Worsman , Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
M.W.T. Wong , Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Hung Hom, China
pp. 84

A methodology for fault model development for hierarchical linear systems (Abstract)

Jun-Weir Lin , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Yin-Chao Huang , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu-E Chen , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chau-Chin Su , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung-Len Lee , Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 90

Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers (Abstract)

V.C. Alves , Brazilian Navy Res. Inst., Brazil
J.V. Calvano , Brazilian Navy Res. Inst., Brazil
M.S. Lubaszewski , Brazilian Navy Res. Inst., Brazil
pp. 96
Session B2: Fault Simulation & Timing Simulation, Chair: Kazumi Hatayama, Hitachi, Japan

A new framework for static timing analysis, incremental timing refinement, and timing simulation (Abstract)

Liang-Chi Chen , Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta , Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
M.A. Breuer , Dept. of Electr. Eng.-Systems, Univ. of Southern California, Los Angeles, CA, USA
pp. 102

On the feasibility of fault simulation using partial circuit descriptions (Abstract)

S.M. Reddy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 108

Fsimac: a fault simulator for asynchronous sequential circuits (Abstract)

M. Roncken , Indian Stat. Inst., Calcutta, India
R. Roy , Indian Stat. Inst., Calcutta, India
S. Sur-Kolay , Indian Stat. Inst., Calcutta, India
P.P. Chaudhuri , Indian Stat. Inst., Calcutta, India
K. Stevens , Indian Stat. Inst., Calcutta, India
pp. 114

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits (Abstract)

Y. Miura , Grad. Sch. of Eng., Osaka Univ., Japan
A. Keshk , Grad. Sch. of Eng., Osaka Univ., Japan
K. Kinoshita , Grad. Sch. of Eng., Osaka Univ., Japan
pp. 120

Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis (Abstract)

S. Steen , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
M. McManus , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
P. Sanda , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
D. Knebel , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
S. Polonsky , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 125
Fringe Meeting
Session C1: Fault Analysis I, Chair: Shiyi Xu, Shanghai University of Science and Technology, China

An experimental analysis of spot defects in SRAMs: realistic fault models and tests (Abstract)

S. Hamdioui , Intel Corp., Santa Clara, CA, USA
A.J. Van de Goor , Intel Corp., Santa Clara, CA, USA
pp. 131

Enhanced untestable path analysis using edge graphs (Abstract)

S. Kajihara , Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
S.M. Reddy , Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
I. Pomeranz , Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
T. Shimono , Depty. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 139

A waveform simulator based on Boolean process (Abstract)

Cheng-Wen Wu , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Xiaoyang Yu , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Lijian Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 145

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction (Abstract)

J. Dworak , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
M.R. Mercer , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
B. Cobb , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
T.-C. Wang , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
L.-C. Wang , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
M.R. Grimaila , Comput. Eng. Group, Texas A&M Univ., College Station, TX, USA
pp. 151
Session C2: Test Generation I, Chair: Yukihiro Iguchi, Meiji University, Japan

Compaction-based test generation using state and fault information (Abstract)

V.D. Agrawal , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
A. Giani , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Shuo Sheng , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M. Hsiao , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 159

Test sequence compaction for sequential circuits with reset states (Abstract)

Y. Higami , Ehime Univ., Matsuyama, Japan
Y. Takamatsu , Ehime Univ., Matsuyama, Japan
K. Kinoshita , Ehime Univ., Matsuyama, Japan
pp. 165

Spirit: satisfiability problem implementation for redundancy identification and test generation (Abstract)

E. Gizdarski , Dept. of Comput. Syst., Rousse Univ., Rousse, Bulgaria
H. Fujiwara , Dept. of Comput. Syst., Rousse Univ., Rousse, Bulgaria
pp. 171

Forecasting the efficiency of test generation algorithms for digital circuits (Abstract)

Shiyi Xu , Sch. of Comput. Sci. & Eng., Shanghai Univ., China
Wei Cen , Sch. of Comput. Sci. & Eng., Shanghai Univ., China
pp. 179
Session C3: Functional Testing, Chair: Tomoo Inoue, Hiroshima University, Japan

Fast hierarchical test path construction for DFT-free controller-datapath circuits (Abstract)

A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Y. Makris , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
J. Collins , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 185

Faster processing for microprocessor functional ATPG (Abstract)

J. Hirase , Matsushita Electr. Ind. Co. Ltd., Japan
S. Yoshimura , Matsushita Electr. Ind. Co. Ltd., Japan
pp. 191

Functional Testing of Microprocessors with Graded Fault Coverage (Abstract)

Rajesh Kannah , ATI Research Silicon Valley Inc, Chennai
C.P. Ravikumar , Indian Institute of Technology, New Delhi
pp. 204
Session D1: Built-in Self-Test I, Chair: Jacob Savir, New Jersey Institute of Technology

Single-control testability of RTL data paths for BIST (Abstract)

M. Izutsu , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Fujiwara , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
H. Wada , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
T. Masuzawa , Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Nara, Japan
pp. 210

A BIST methodology for at-speed testing of data communications transceivers (Abstract)

S.L. Lin , Intelligent Micro Inc., San Jose, CA, USA
S. Mourad , Intelligent Micro Inc., San Jose, CA, USA
S. Krishnan , Intelligent Micro Inc., San Jose, CA, USA
pp. 216

High-speed generation of LFSR signatures (Abstract)

Ming-Der Shieh , Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Ming-Hwa Sheu , Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Hsin-Fu Lo , Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
pp. 222
Session D2: Software Testing & Test Synthesis, Chair: Wen-Ben Jone, national Chung Cheng University, Taiwan

Strong self-testability for data paths high-level synthesis (Abstract)

H. Fujiwara , Dept. of Comput. Sci., Beijing Univ., China
T. Masuzawa , Dept. of Comput. Sci., Beijing Univ., China
Xiaowei Li , Dept. of Comput. Sci., Beijing Univ., China
pp. 229

Generating test items for checking illegal behaviors in software testing (Abstract)

T. Yamamoto , Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
M. Hirayama , Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
O. Mizuno , Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
J. Okayasu , Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
T. Kikuno , Res. & Dev. Center, Toshiba Corp., Tokyo, Japan
pp. 235

Using genetic algorithms for test case generation in path testing (Abstract)

Jin-Cherng Lin , Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan
Pu-Lin Yeh , Dept. of Comput. Sci. & Eng., Tatung Univ., Taipei, Taiwan
pp. 241
Session D3: Embedded-Core Testing, Chair: Douglas Kay, Cisco, USA

A hierarchical test control architecture for core based design (Abstract)

Cheng-I Huang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 248

Embedded core testing using genetic algorithms (Abstract)

Ruofan Xu , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M.S. Hsiao , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 254

Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems (Abstract)

R.A. Parekhji , Texas Instrum. Ltd., Bangalore, India
A. Bagwe , Texas Instrum. Ltd., Bangalore, India
pp. 260
Session E1: Memory Testing, Chair: Rubin A. Parekhji, TI, India

Detection of SRAM cell stability by lowering array supply voltage (Abstract)

Hung-Wen Chang , Taiwan Semicond. Manuf. Co., Taiwan
Yung-Fa Chou , Taiwan Semicond. Manuf. Co., Taiwan
Hung-Jen Liao , Taiwan Semicond. Manuf. Co., Taiwan
Ding-Ming Kwai , Taiwan Semicond. Manuf. Co., Taiwan
Ching-Hua Chiao , Taiwan Semicond. Manuf. Co., Taiwan
pp. 268

A realistic fault model for flash memories (Abstract)

Yea-Ling Horng , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Jing-Reng Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Tsin-Yuan Chang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 274

Impact of memory cell array bridges on the faulty behavior in embedded DRAMs (Abstract)

A.J. van de Goor , Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Zaid Al-Ars , Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
pp. 282

Memory test time reduction by interconnecting test items (Abstract)

Wen-Jer Wu , Cadence Design Syst., Hsin-Chu, Taiwan
Chuan Yi Tang , Cadence Design Syst., Hsin-Chu, Taiwan
pp. 290

An efficient parallel transparent diagnostic BIST (Abstract)

W.B. Jone , Dept. of CS&IE, Nat. Chung-Cheng Univ., Taiwan
D.C. Huang , Dept. of CS&IE, Nat. Chung-Cheng Univ., Taiwan
pp. 299
Session E2: Test Generation II, Chair: Christian Landrault, LIRMM, France

Test generation for crosstalk-induced faults: framework and computational results (Abstract)

M.A. Breuer , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Wei-Yu Chen , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
S.K. Gupta , Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 305

Testing programmable interconnect systems: an algorithmic approach (Abstract)

W.K. Huang , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
B. Liu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 311

Reducing test application time for full scan circuits by the addition of transfer sequences (Abstract)

S.M. Reddy , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
I. Pomeranz , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 317

TOF: a tool for test pattern generation optimization of an FPGA application oriented test (Abstract)

J. Figueras , LIRMM-UM2, Montpellier, France
J.M. Portal , LIRMM-UM2, Montpellier, France
M. Renovell , LIRMM-UM2, Montpellier, France
P. Faure , LIRMM-UM2, Montpellier, France
Y. Zorian , LIRMM-UM2, Montpellier, France
pp. 323

Formal verification of data-path circuits based on symbolic simulation (Abstract)

T. Toneda , Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
Y. Morihiro , Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
pp. 329
Session E3: IDDQ Testing, Chair: Sying-Jyan Wang, National Chung Hsing University, Taiwan

Is IDDQ testing not applicable for deep submicron VLSI in year 2011? (Abstract)

Chauchin Su , Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Chih-Wen Lu , Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Chung Len Lee , Dept. of Electr. Eng., Da Yeh Univ., Taiwan
Jwu-E Chen , Dept. of Electr. Eng., Da Yeh Univ., Taiwan
pp. 338

High speed IDDQ test and its testability for process variation (Abstract)

H. Yotsuyanagi , Fac. of Eng., Tokushima Univ., Japan
M. Takeda , Fac. of Eng., Tokushima Univ., Japan
M. Hashizume , Fac. of Eng., Tokushima Univ., Japan
T. Tamesada , Fac. of Eng., Tokushima Univ., Japan
M. Ichimiya , Fac. of Eng., Tokushima Univ., Japan
pp. 344

Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults (Abstract)

K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
T. Maeda , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 350

A high-speed IDDQ sensor implementation (Abstract)

S. Nishikawa , Test Eng. Center, Sharp Corp., Nara, Japan
T. Inufushi , Test Eng. Center, Sharp Corp., Nara, Japan
K. Kinoshita , Test Eng. Center, Sharp Corp., Nara, Japan
Y. Antonioli , Test Eng. Center, Sharp Corp., Nara, Japan
pp. 356

Cyclic greedy generation method for limited number of IDDQ tests (Abstract)

T. Shinogi , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
M. Ushio , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
T. Hayashi , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
pp. 362
Session F1: Built-in Self-Test II, Chair: Shianling Wu, Lucent, USA

Accelerated test pattern generators for mixed-mode BIST environments (Abstract)

Wei-Lun Wang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 368

Effective parallel processing techniques for the generation of test data for a logic built-in self test system (Abstract)

B. Keller , Intel Texas Design Center, Austin, TX, USA
S. Paliwal , Intel Texas Design Center, Austin, TX, USA
P. Chang , Intel Texas Design Center, Austin, TX, USA
pp. 374

Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata (Abstract)

M. Kopec , Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
A. Hlawiczka , Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
pp. 380

An efficient BIST design using LFSR-ROM architecture (Abstract)

Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Lijian Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 386
Session F2: Testability Analysis and Design for Testability, Chair: Xinghao Chen, IBM, USA

Novel techniques for improving testability analysis (Abstract)

Yin-He Su , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Shih-Chieh Chang , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Ching-Hwa Cheng , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 392

A class of sequential circuits with combinational test generation complexity under single-fault assumption (Abstract)

E. Gizdarski , Nara Inst. of Sci. & Technol., Japan
M. Inoue , Nara Inst. of Sci. & Technol., Japan
H. Fujiwara , Nara Inst. of Sci. & Technol., Japan
pp. 398

Design for sequential testability: an internal state reseeding approach for 100 % fault coverage (Abstract)

C. Landrault , Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
M.L. Flottes , Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
A. Petitqueux , Lab. d'Inf. de Robotique et de Microelectron., Montpellier, France
pp. 404
Session F3: Fault Tolerance, Chair: J.C. Frank Lien, Actel, USA

Testing approach within FPGA-based fault tolerant systems (Abstract)

A. Doumar , Dept. of Inf. & Image Sci., Chiba Univ., Japan
H. Ito , Dept. of Inf. & Image Sci., Chiba Univ., Japan
pp. 411

Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis (Abstract)

F. Vargas , Dept. of Electr. Eng., Catholic Univ., Porto Alegre, Brazil
A. Amory , Dept. of Electr. Eng., Catholic Univ., Porto Alegre, Brazil
pp. 417

Fault tolerant multistage interconnection networks with widely dispersed paths (Abstract)

N. Kamiura , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
T. Kodera , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
N. Matsui , Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
pp. 423
Session G1: Fault Analysis II, Chair: Mike Wong, Hong Kong Polytechnic University, Hong Kong

Charge sharing fault analysis and testing for CMOS domino logic circuits (Abstract)

Shih-Chieh Chang , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Ching-Hwa Cheng , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Jinn-Shyan Wang , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
Wen-Ben Jone , Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
pp. 435

Testing domino circuits in SOI technology (Abstract)

N.A. Touba , Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
E. MacDonald , Adv. PowerPC Dev., IBM Corp., Austin, TX, USA
pp. 441
Session G2: Low-Power Testing, Chair: C.P. Ravikumar, Indian Institute of Technology, India

Peak-power reduction for multiple-scan circuits during test application (Abstract)

Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Tsung-Chu Haung , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Jih-Jeen Chen , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 453

An adjacency-based test pattern generator for low power BIST design (Abstract)

L. Guiller , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Girard , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 459

Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling (Abstract)

Xiaojun Wang , Dublin City Univ., Ireland
V. Murescan , Dublin City Univ., Ireland
M. Vladutiu , Dublin City Univ., Ireland
pp. 465
Session G3: Self-Checking Circuits and Concurrent Fault Detection, Chair: Yinghua Min, Academia Sinica, China

A method for determining whether asynchronous circuits are self-checking (Abstract)

M.J. Liebelt , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
Cheng-Chew Lim , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 472

On testing safety-sensitive digital systems (Abstract)

J. Savir , Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
pp. 478

Accumulation-based concurrent fault detection for linear digital state variable systems (Abstract)

I. Bayraktaroglu , California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , California Univ., San Diego, La Jolla, CA, USA
pp. 484
Tutorial 1
Tutorial 2

Author Index (PDF)

pp. 493
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