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2012 IEEE 21st Asian Test Symposium (1999)
Shanghai, China
Nov. 16, 1999 to Nov. 18, 1999
ISSN: 1081-7735
ISBN: 0-7695-0315-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. xix
Plenary Session: Keynote Address
Session 1A: ATPG Related Approaches I, Chair: Christian Landrault, LIRMM, France

A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description (Abstract)

Satoshi Ohtake , Nara Institute of Science and Technology
Michiko Inoue , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 5

Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors (Abstract)

Tomohisa Sczaki , Matsushita Electric Industrial Co., Ltd
Junichi Hirase , Matsushita Electric Industrial Co., Ltd
Shinichi Yoshimura , Matsushita Electric Industrial Co., Ltd
pp. 13

On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits (Abstract)

Tomohisa Kaneko , Kyushu Institute of Technology
Seiji Kajihara , Kyushu Institute of Technology
Atsushi Murakami , Kyushu Institute of Technology
pp. 20

Identification of Feedback Bridging Faults with Oscillation (Abstract)

Takeomi Tamesada , University of Tokushima
Hiroyuki Yotsuyanagi , University of Tokushima
Masaki Hashizume , University of Tokushima
pp. 25
Session 1B: Delay Fault & Memory Test, Chair: Xinghao Chen, IBM, USA

Defining SRAM Resistive Defects and Their Simulation Stimuli (Abstract)

J.E. Simonse , Delft University of Technology
A.J. van de Goor , Delft University of Technology
pp. 33

Vector-Based Functional Fault Models for Delay Faults (Abstract)

Irith Pomeranz , University of Iowa
Sudhakar M. Reddy , University of Iowa
pp. 41

Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers (Abstract)

H.T. Vergos , University of Patras and Computer Technology
D. Nikolos , University of Patras and Computer Technology
G. Sidiropoulos , University of Patras and Computer Technology
pp. 47

March Tests for Word-Oriented Two-Port Memories (Abstract)

A. J. van de Goor , Delft University of Technology
Said Hamdioui , Intel Corporation and Delft University of Technology
pp. 53
Session 2A: ATPG Related Approaches II, Chair: Sreejit Chakravarty, Intel, USA

Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits (Abstract)

Hefeng Cao , National University of Defense Technology
Zhide Zeng , National University of Defense Technology
Jihua Chen , National University of Defense Technology
pp. 70
Session 2B: BIST Related Approaches, Chair: Yuejian Wu, Nortel Semiconductor, Canada

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption (Abstract)

P. Girard , Universit? Montpellier II
S. Pravossoudovitch , Universit? Montpellier II
L. Guiller , Universit? Montpellier II
C. Landrault , Universit? Montpellier II
pp. 89

A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD (Abstract)

F. Lombardi , Northeastern University
W. Feng , Lucent Technologies
F.J. Meyer , Northeastern University
W.K. Huang , Fudan University
pp. 95

Accelerating Test Data Processing (Abstract)

Kenneth Lever , Massey University
Serge Demidenko , Massey University
pp. 113
Session 3A: Test Generation, Diagnosis, & Verification, Chair: Hiromi Hiraishi, Kyoto Sangyo University, Japan

Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits (Abstract)

Kozo Kinoshita , Osaka University
Yukiya Miura , Tokyo Metropolitan University
Arabi Keshk , Osaka University
pp. 121

A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers (Abstract)

Raghvendra G. Deshmukh , Florida Institute of Technology
Chanyutt Arjhan , Florida Institute of Technology
pp. 127

A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits (Abstract)

Zhide Zeng , National University of Defense Technology
Jihua Chen , National University of Defense Technology
Pengxia Liu , National University of Defense Technology
pp. 133
Session 3B: IDDQ Test, Chair: Dajin Wang, University of Montclair, USA

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits (Abstract)

Yoshinobu Higami , Ehime University
Yuzo Takamatsu , Ehime University
Kewal K. Saluja , University of Wisconsin
Kozo Kinoshita , Osaka University
pp. 141

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits (Abstract)

Kozo Kinoshita , Osaka University
Seiji Kajihara , Kyushu Institute of Technology
Hideyuki Ichihara , Osaka University
pp. 147

Scan Chain Diagnosis Using IDDQ Current Measurement (Abstract)

Naoki Shindou , Matsushita Electric Industrial Co., Ltd
Kouji Akahori , Matsushita Electronics Industrial Co., Ltd
Junichi Hirase , Matsushita Electric Industrial Co., Ltd
pp. 153

IDDQ Current Dependency on Test Vectors and Bridging Resistance (Abstract)

Kozo Kinoshita , Osaka University
Arabi Keshk , Osaka University
Yukiya Miura , Tokyo Metropolitan University
pp. 158
Session 4A: Sequential Circuit Test, Chair: Serge Demidenko, Massey University, New Zealand

Genetic Algorithm Based Test Generation for Sequential Circuits (Abstract)

Li Shen , Chinese Academy of Sciences
pp. 179

Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation (Abstract)

Mario Konijnenburg , Philips Research Laboratories
Hans Van der Linden , Delft University of Technology
Ad van de Goor , Delft University of Technology
pp. 185

Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Toshihiro Hiraoka , Matsushita Electric Industrial Co., Ltd.
Tomoo Inoue , Nara Institute of Science and Technology
Toshinori Hosokawa , Matsushita Electric Industrial Co., Ltd.
pp. 192
Session 4B: Fault-Tolerant & Diagnosis, Chair: Xiaozhong Yang, Harbin Institute of Technology, China

Activation Function Manipulation for Fault Tolerant Feedforward Neural Networks (Abstract)

Yutaka Hata , Himeji Institute of Technology
Yasuyuki Taniguchi , Himeji Institute of Technology
Naotake Kamiura , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
pp. 203

Fault-Tolerant Analysis of Feedback Neural Networks with Threshold Neurons (Abstract)

Shiyuan Yang , Tsinghua University
Dongcheng Hu , Tsinghua University
Tao Zhang , Tsinghua University
pp. 209

Fault-Tolerant Strategies and Their Design Methods for Application Software (Abstract)

Shihuang Shao , China Textile University
Jianhua Gao , China Textile University
pp. 214

Test by Distributed Monitoring (Abstract)

Chenglian Peng , Fudan University
Baifeng Wu , Fudan University
Xiaoguang Sun , Fudan University
pp. 218
Session 5A: Analog Circuits Test, Chair: Chung-Len Lee, National Chiao Tung University, Taiwan

Optimized Statistical Analog Fault Simulation (Abstract)

Abdelhakim Khouas , University of Pierre et Marie Curie
Anne Derieux , University of Pierre et Marie Curie
Mohamed Dessouky , University of Pierre et Marie Curie
pp. 227

Analog Metrology and Stimulus Selection in a Noisy Environment (Abstract)

Chung-Len Lee , National Chiao Tung University
Yue-Tsang Chen , National Central University
Chauchin Su , National Central University
pp. 233

Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems (Abstract)

Sam Huynh , University of Washington
Mani Soma , University of Washington
Seongwon Kim , University of Washington
Giri Devarayanadurg , University of Washington
Jinyan Zhang , University of Washington
pp. 239
Session 5B: (Special Session) Railway Signaling Software Testing, Chair: Yinghua Min, ICT of China, China

A Novel Testing Approach for Safety-Critical Software (Abstract)

Fangmei Wu , Shanghai Tiedao University
Zhongwei Xu , Shanghai Tiedao University
pp. 251

How to Design an Environment Simulator for Safety Critical Software Testing (Abstract)

Haiying Tu , Shanghai Tiedao University
Fangmei Wu , Shanghai Tiedao University
pp. 256
Session 6A: DFT, Chair: Kiyoshi Furuya, Chuo University, Japan

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency (Abstract)

Satoshi Ohtake , Nara Institute of Science and Technology
Debesh Kumar Das , Jadavpur University
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 263

An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets (Abstract)

Abhijit Jas , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
Kartik Mohanram , University of Texas at Austin
pp. 275
Session 6B: Software Test & Verification, Chair: Kuen-Jong Lee, National Cheng Kung University, Taiwan

Scenario Based Integration Testing for Object-Oriented Software Development (Abstract)

Youngchul Kim , Illinois Institute of Technology
C. Robert Carlson , Illinois Institute of Technology
pp. 283

An Approach to Testing the Nonexistence of Initial State in Z Specifications (Abstract)

Huaikou Miao , Shanghai University
Xiaolei Gao , Shanghai University
Ling Liu , Shanghai University
pp. 289

Generating Test Cases for Real-Time Software by Time Petri Nets Model (Abstract)

Jin-Cherng Lin , Tatung Institute of Technology
Ian Ho , Tatung Institute of Technology
pp. 295

Defect Level Prediction Using Multi-Model Fault Coverage (Abstract)

Tsung-Ying Lee , Fu Jen Catholic University
Cheng-Wen Wu , National Tsing Hua University
Shyue-Kung Lu , Fu Jen Catholic University
pp. 301
Session 7A: Scan & Boundary Scan, Chair: T.W. Williams, Synopsys, Inc.

A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure (Abstract)

Tomoya Takasaki , Nara Institute of Science and Technology
Tomoo Inoue , Hiroshima City University
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 309

An Input Control Technique for Power Reduction in Scan Circuits During Test Application (Abstract)

Tsung-Chu Huang , National Cheng-Kung University
Kuen-Jong Lee , National Cheng-Kung University
pp. 315

A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor (Abstract)

Xinghao Chen , IBM Corporation
Joe Swenton , IBM Corporation
Ron Walther , IBM Corporation
Tom Snethen , IBM Corporation
pp. 321

A New Algorithm for Retiming-Based Partial Scan (Abstract)

Zhigang Mao , Harbin Institute of Technology
Zulan Huang , Harbin Institute of Technology
Yizheng Ye , Harbin Institute of Technology
pp. 327
Session 7B: (Special Session) Beam Testing in Japan, Chair: Hiromu Fujioka, Osaka University, Japan

Intelligent EB Test System for Automatic VLSI Fault Tracing (Abstract)

Hiromu Fujioka , Osaka University
Katsuyoshi Miura , Osaka University
Koji Nakamae , Osaka University
pp. 335

Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits (Abstract)

Kiyokazu Nishi , Matsushita Electric Industrial Co., Ltd.
Reisuke Shimoda , Matsushita Electric Industrial Co., Ltd.
Takaki Yoshida , Matsushita Electric Industrial Co., Ltd.
Masafumi Watari , Matsushita Electric Industrial Co., Ltd.
Akira Motohara , Matsushita Electric Industrial Co., Ltd.
Yasuhiro Toyota , Matsushita Electric Industrial Co., Ltd.
pp. 347
Session 8A: FPGA Test, Chair: Hideo Fujiwara, Nara Institute of Science & Technology, Japan

Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs (Abstract)

Wei Kang Huang , Fudan University
Fabrizio Lombardi , Northeastern University
Jian Xu , Fudan University
Yinlei Yu , Fudan University
pp. 357

IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs (Abstract)

Lan Zhao , Lucent Technologies
D.M.H. Walker , Texas A&M University
Fabrizio Lombardi , Northeastern University
pp. 375
Session 8B: (Special Session) Beam Testing in Japan, Chair: Kiyoshi Nikawa, NEC, Japan

High Resolution CD-SEM System (Abstract)

Hideo Todokoro , Hitachi, Ltd., Hitachinaka, Japan
Yoichi Ose , Hitachi, Ltd., Hitachinaka, Japan
Makoto Ezumi , Hitachi, Ltd., Hitachinaka, Japan
pp. 383

Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method (Abstract)

Shoji Inoue , T.D.I. Co., Ltd.,
Kiyoshi Nikawa , NEC Corporation
Shinya Sone , Naito Densei Kogyo, Co., Ltd.
Kazuyuki Morimoto , Naito Densei Kogyo, Co., Ltd.
pp. 394
Panel Session 1
Panel Session 2

Author Index (PDF)

pp. 405
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