The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (1997)
Akita, JAPAN
Nov. 17, 1997 to Nov. 18, 1997
ISSN: 1081-7735
ISBN: 0-8186-8209-4
TABLE OF CONTENTS

Reviewers (PDF)

pp. xv
Plenary Session: Keynote Address
Session 1A: Test Generation I, Chair: J. Savir, New Jersey Institute of Technology, USA

On the Adders with Minimum Tests (Abstract)

Seiji Kajihara , Kyushu Institute of Technology
Tsutomu Sasao , Kyushu Institute of Technology
pp. 10

Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL (Abstract)

Tsuyoshi Shinogi , Faculty of Engineering, Mie University
Terumine Hayashi , Faculty of Engineering, Mie University
Kazuo Taki , Faculty of Engineering, Kobe University
pp. 16

An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits (Abstract)

Noroyoshi Itazaki , Applied Physics, Osaka Univ.
Yasutaka Idomoto , Applied Physics, Osaka Univ.
Kozo Kinoshita , Applied Physics, Osaka Univ.
pp. 22
Session 1B: Design for Testability I, Chair: S.K. Jhajharia, Singapore Polytechnic, Singapore

Guaranteeing Testability in Re-encoding for Low Power (Abstract)

F. Corno , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
S. Chiusano , Politecnico di Torino
P. Prinetto , Politecnico di Torino
pp. 30

Design of C-Testable Multipliers Based on the Modified Booth Algorithm (Abstract)

Yuzo Takamatsu , Faculty of Engineering, Ehime University
Hiroshi Takahashi , Faculty of Engineering, Ehime University
Kwame Osei Boateng , Faculty of Engineering, Ehime University
pp. 42

Testability Prediction for Sequential Circuits Using Neural Network (Abstract)

Bole Shi , Fudan University
Percy G. Dias , Fudan University
Shiyi Xu , Shanghai University of Science and Technology
Peter Waignjo , Shanghai University of Science and Technology
pp. 48
Session 2A: Test Generation II, Chair: B. Kaminska, OPMAXX, USA

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits (Abstract)

M. Sonza Reorda , Politecnico di Torino
G. Squillero , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
F. Corno , Politecnico di Torino
P. Prinetto , Politecnico di Torino
pp. 56

Sequential Test Generation Based on Circuit Pseudo-Transformation (Abstract)

Tomoo Inoue , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 62

Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG (Abstract)

M. Violante , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
F. Corno , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
P. Prinetto , Politecnico di Torino
pp. 68
Session 2B: Fault Tolerance, Chair: N. Kanekawa, Hitachi, Japan

On fault injection approaches for fault tolerance of feedforward neural networks (Abstract)

T. Ito , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
I. Takanami , Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
pp. 88

A concurrent fault-detection scheme for FFT processors (Abstract)

T. Kabasawa , Niigata Inst. of Technol., Japan
M. Uenoyama , Niigata Inst. of Technol., Japan
M. Tsunoyama , Niigata Inst. of Technol., Japan
pp. 94

Code-Disjoint Circuits for Parity Circuits (Abstract)

Egor S. Sogomonyan , Russian Academy of Sciences
Michael Goessel , University of Potsdam
Hendrik Hartje , University of Potsdam
pp. 100
Session 3A: Special Session I - Case Studies for DFT Techniques in Japanese Industry, Chair & Coordinator, M. Yoshida, NEC, Japan

Testability Features of R10000 Microprocessor (Abstract)

Dave Burns , Silicon Graphics Inc.
Ben Mathew , Silicon Graphics Inc.
Yeuk-Hai Mok , Silicon Graphics Inc.
Junji Mori , Toshiba Corp.
pp. 108

Application of a Design for Delay Testability Approach to High Speed Logic LSIs (Abstract)

M. Ikeda , Hitachi Research Laboratory, Hitachi, Ltd.
S. Uchiyama , Hitachi Engineering, Co. Ltd.
Y. Sakamoto , Hitachi Information Technology, Co. Ltd.
K. Hatayama , Hitachi Research Laboratory, Hitachi, Ltd.
M. Takakura , Hitachi Engineering, Co. Ltd.
pp. 112

An effective fault simulation method for core based LSI (Abstract)

T. Yoshida , Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
T. Mizokawa , Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
R. Shimoda , Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
K. Hirayama , Corporate Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Kyoto, Japan
pp. 116

Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs (Abstract)

Yoshiyuki Nakamura , NEC Corporation, ULSI Systems Development Laboratories
Hitoshi Hikima , NEC Corporation, ULSI Systems Development Laboratories
Kazuo Wakui , NEC Corporation, ULSI Systems Development Laboratories
Toshinobu Ono , NEC Corporation, ULSI Systems Development Laboratories
Masaaki Yoshida , NEC Corporation, ULSI Systems Development Laboratories
pp. 122

ATREX : Design for Testability System for Mega Gate LSIs (Abstract)

Junko Kumagai , Fujitsu Limited
Takashi Aikyo , Fujitsu Limited
Tomoko Anan , Fujitsu Lsi Tecnology Limited
Junichi Niimi , Fujitsu Lsi Tecnology Limited
Koichi Itaya , Fujitsu Limited
Michiaki Emori , Fujitsu Limited
pp. 126
Session 3B: Test Technologies, Chair: M. Nishihara, IBM Japan

On energy efficiency of VLSI testing (Abstract)

Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 132

ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs (Abstract)

Marcel Jacomet , Biel School of Engineering
Lukas Winzenried , Biel School of Engineering
Roger Waelti , Biel School of Engineering
Jaime Perez , Biel School of Engineering
Martin Gysel , Biel School of Engineering
pp. 138

Computing stress tests for interconnect defects (Abstract)

V. Dabholkar , Motorola Inc., Austin, TX, USA
S. Chakravarty , Motorola Inc., Austin, TX, USA
pp. 143

Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits (Abstract)

Hideo Tamamoto , Akita University
Josep Altet , Universitat Politecnica de Catalunya
Antonio Rubio , Universitat Politecnica de Catalunya
pp. 149

A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register (Abstract)

Z.M. Darus , Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia
I. Ahmed , Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia
L. Ali , Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia
pp. 155
Session 4A: Special Session II - Beam Testing of VLSI Circuits in Japan, Chair: K. Nikawa, NEC, Japan

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data (Abstract)

Koji Nakamae , Faculty of Engineering, Osaka University
Kohei Nakata , Faculty of Engineering, Osaka University
Katsuyoshi Miura , Faculty of Engineering, Osaka University
Hiromu Fujioka , Faculty of Engineering, Osaka University
pp. 162

An approach to diagnose logical faults in partially observable sequential circuits (Abstract)

K. Yamazaki , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
T. Yamada , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
pp. 168

Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits (Abstract)

Norio Kuji , NTT System Electronics Laboratories
pp. 174
Session 4B: Mixed-Signal Test, Chair: C.W. Wu, National Tsing Hua University, Taiwan

A perturbation based fault modeling and simulation for mixed-signal circuits (Abstract)

B. Kaminska , OPMAXX Inc., Beaverton, OR., USA
K. Saab , OPMAXX Inc., Beaverton, OR., USA
D. Marche , OPMAXX Inc., Beaverton, OR., USA
N. Ben-Hamida , OPMAXX Inc., Beaverton, OR., USA
pp. 182

Static Testing of ADCs Using Wavelet Transforms (Abstract)

Takahiro Yamaguchi , Advantest Laboratories Ltd.
pp. 188

Analog signal metrology for mixed signal ICs (Abstract)

Yi-Ren Cheng , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shing Tenchen , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Yue-Tsang Chen , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 194
Session 5A: Special Session III - Novel Beam Testing Techniques in Japan, Chair: M. Miyoshi, Toshiba, Japan

A New Auto-Focus Method in Critical Dimension Measurement SEM (Abstract)

M. Miyoshi , Toshiba Corp.
F. Komatsu , Toshiba Corp.
H. Motoki , Toshiba Corp.
pp. 202

Novel Optical Probing System for Quarter-micron VLSI Circuits (Abstract)

Y. Goto , Fujitsu Laboratories Ltd.
S. Wakana , Fujitsu Laboratories Ltd.
J. Matsumoto , Advantest Corporation
H. Sekiguchi , Fujitsu Laboratories Ltd.
Y. Umehara , Advantest Corporation
K. Ozaki , Fujitsu Laboratories Ltd.
pp. 208
Session 5B: Decision Diagrams and Logic Optimization; Coordinator: H. Fujioka, Osaka University, Japan

A variable reordering method for fast optimization of binary decision diagrams (Abstract)

Hoon Chang , Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea
Moon-Bae Song , Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea
pp. 228

On Decomposition of Kleene TDDs (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology
Munehiro Matsuura , Kyushu Institute of Technology
Yukihiro Iguchi , Meiji University
pp. 234
Session 6A: FPGA Test, Chair: S. Xu, Shanghai University of Science and Technology, China

Testing for the programming circuit of LUT-based FPGAs (Abstract)

H. Michinishi , Dept. of Inf. Technol., Okayama Univ., Japan
T. Yokohira , Dept. of Inf. Technol., Okayama Univ., Japan
T. Inoue , Dept. of Inf. Technol., Okayama Univ., Japan
T. Okamoto , Dept. of Inf. Technol., Okayama Univ., Japan
H. Fujiwara , Dept. of Inf. Technol., Okayama Univ., Japan
pp. 242

A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs (Abstract)

F.J. Meyer , Texas A&M University
F. Lombardi , Texas A&M University
W.K. Huang , Fudan University
M.Y. Zhang , Fudan University
pp. 248

Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA (Abstract)

M. Renovell , LIRMM-UMII
J. Figueras , Universitat Polytechnica de Catalunya
J.M. Portal , LIRMM-UMII
Y. Zorian , Logic Vision Inc.
pp. 254
Session 6B: Software Test, Chair: T. Yoneda, Tokyo Institute of Technology, Japan

Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net Model (Abstract)

Osamu Mizuno , Osaka University
Shinji Kusumoto , Osaka University
Yasunari Takagi , OMRON Corporation, Japan
Tohru Kikuno , Osaka University
Keishi Sakamoto , OMRON Corporation, Japan
pp. 269
Session 7A: Diagnosis, Chair: Y. Min, Chinese Academy of Sciences, China

On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs (Abstract)

Tomoo Inoue , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
Satoshi Miyazaki , Nara Institute of Science and Technology
pp. 276

Fault Diagnosis for Static CMOS Circuits (Abstract)

Wen Xiaoqing , Dept. of Information Engineering, Akita 010, Japan
pp. 282

Fault diagnosis of odd-even sorting networks (Abstract)

J.E. Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wen Ching Wu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chih Wei Hu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 288
Session 7B: Design for Testability II, Chair: A. Ivanov, University of British Columbia, Canada

Test Compaction in a Parallel Access Scan Environment (Abstract)

Prab Varma , Duet Technologies Inc.
Sandeep Bhatia , Duet Technologies Inc.
pp. 300
Session 8A: Delay Test, Chair: C. Landrault, LIRMM, France

On the capability of delay tests to detect bridges and opens (Abstract)

S. Chakravarty , Intel Corp., Santa Clara, CA, USA
pp. 314

Memory Efficient ATPG for Path Delay Faults (Abstract)

Shiyuan Yang , Tsinghua University
Wangning Long , Tsinghua University
Zhongcheng Li , Chinese Academy of Science
Yinghua Min , Chinese Academy of Science
pp. 326

Design of delay-verifiable combinational logic by adding extra inputs (Abstract)

Xiaoming Yu , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 332
Session 8B: Built-in Self-Test I, Chair: K. Iwasaki, Tokyo Metropolitan University, Japan

BIST testability enhancement using high level test synthesis for behavioral and structural designs (Abstract)

C.A. Papachristou , Rockwell Semicond. Syst., Newport Beach, CA, USA
Kowen Lai , Rockwell Semicond. Syst., Newport Beach, CA, USA
M. Baklashov , Rockwell Semicond. Syst., Newport Beach, CA, USA
pp. 338

On Chip Weighted Random Patterns (Abstract)

Jacob Savir , New Jersey Institute of Technology
pp. 343

Random Pattern Testable Design with Partial Circuit Duplication (Abstract)

Hiroshi Yokoyama , Mining College, Akita University
Hideo Tamamoto , Mining College, Akita University
Xiaoqing Wen , Mining College, Akita University
pp. 353

Accelerated Test Points Selection Method for Scan-Based BIST (Abstract)

Isao Higashi , General Purpose Computer Division, Hitachi, Ltd.,
Michinobu Nakao , Hitachi Research Laboratory, Hitachi, Ltd.
Kazumi Hatayama , Hitachi Research Laboratory, Hitachi, Ltd.
pp. 359
Session 9A: Current Testing, Chair: J.E. Chen, Chung-Hua Polytechnic Institute, Taiwan

Power supply current monitoring techniques for testing PLLs (Abstract)

M. Dalmia , Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
A. Ivanov , Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
S. Tabatabaei , Dept. of Electr. & Comput. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 366

Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates (Abstract)

Takeomi Tamesada , The Univ. of Tokushima
Masaki Hashizume , The Univ. of Tokushima
Toshimasa Kuchii , The Univ. of Tokushima
pp. 372

IDDT Testing (Abstract)

Yinghua Min , Institute of Computing Technology, Chinese Academy of Sciences
Zhongcheng Li , Institute of Computing Technology, Chinese Academy of Sciences
Zhuxing Zhao , Institute of Computing Technology, Chinese Academy of Sciences
pp. 378

Built-in current sensor designs based on the bulk-driven technique (Abstract)

Min-Cheng Huang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Tsung-Chu Huang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 384
Session 9B: Built-in Self-Test II, Chair: T. Tada, Mitsubishi, Japan

Built-In Self-Test for Multi-Port RAMs (Abstract)

Yuejian Wu , Northern Telecom., Ltd.
Sanjay Gupta , Northern Telecom., Ltd.
pp. 398

An extended march test algorithm for embedded memories (Abstract)

Hoon Chang , Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea
Gang-Min Park , Dept. of Comput. Sci., Soongsil Univ., Seoul, South Korea
pp. 404

Low Cost Bist for Edac Circuits (Abstract)

Dariusz Badura , Silesian University of Katowice
Andrzej Hlawiczka , Silesian Technical University of Gliwice
pp. 410

Author Index (PDF)

pp. 416
142 ms
(Ver 3.1 (10032016))