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2012 IEEE 21st Asian Test Symposium (1996)
Hsinchu, TAIWAN
Nov. 20, 1996 to Nov. 22, 1996
ISSN: 1081-7735
ISBN: 0-8186-7478-4
TABLE OF CONTENTS

Reviewers (PDF)

pp. xviii
Plenary Session: Keynote Speech
Session 1A: Test Pattern Generation

Redundancy Identification Using Transitive Closure (Abstract)

Michael L. Bushnell , Rutgers University
Qing Lin , Sun Microsystems
Vishwani D. Agrawal , Bell Labs Lucent Technologies
pp. 4

Invalid State Identification for Sequential Circuit Test Generation (Abstract)

Hsing-Chung Liang , National Chiao Tung University
Chung Len Lee , National Chiao Tung University
Jwu E Chen , National Chiao Tung University
pp. 10

Hierarchical Test Generation with Built-In Fault Diagnosis (Abstract)

Jan Van Campenhout , University of Ghent
Dirk Stroobandt , University of Ghent
pp. 22

Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors (Abstract)

A.J. van de Goor , Delft University of Technology
J.T. van der Linden , Delft University of Technology
M.H. Konijnenburg , Delft University of Technology
pp. 29
Session 1B: Board and System-Level Test

Hybrid Pin Control Using Boundary-Scan And Its Applications (Abstract)

Wuudiann Ke , Lucent Technologies Bell Labs.
pp. 44

Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Jin-Hua Hong , National Tsing Hua University
Chung-Hung Tsai , National Tsing Hua University
pp. 50

Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems (Abstract)

Sying-Jyan Wang , Holtek Microelectron. Inc., Hsinchu, Taiwan
Po-Ching Hsu , Holtek Microelectron. Inc., Hsinchu, Taiwan
pp. 56

Syndrome Simulation And Syndrome Test For Unscanned Interconnects (Abstract)

Chauchin Su , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Shen Hwang , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Yuan-Tzu Ting , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Shyh-Jye Jou , Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
pp. 62

A Test Methodology for Interconnect Structures of LUT-based FPGAs (Abstract)

Hiroyuki Michinishi , Okayama University
Tokumi Yokohira , Okayama University
Hideo Fujiwara , Nara Institute of Science and Technology
Tomoo Inoue , Nara Institute of Science and Technology
Takuji Okamoto , Okayama University
pp. 68

Testable Design and Testing of MCMs Based on Multifrequency Scan (Abstract)

Wang-Dauh Tseng , National Chiao Tung University
Kuochen Wang , National Chiao Tung University
pp. 75
Session 2A: Design for Testability

A Consistent Scan Design System for Large-Scale ASICs (Abstract)

Seiken Yano , NEC Corporation
Kazushi Nakamura , NEC Corporation
Tatsushige Bitoh , NEC Corporation
Yoshihiro Konno , NEC Corporation
Koji Saga , NEC Corporation
pp. 82

A Design for testability Method Using RTL Partitioning (Abstract)

Toshinori Hosokawa , Matsushita Electric Industrial Co., Ltd.
Kenichi Kawaguchi , Matsushita Electric Industrial Co., Ltd.
Michiaki Muraoka , Matsushita Electric Industrial Co., Ltd.
Mitsuyasu Ohta , Matsushita Electric Industrial Co., Ltd.
pp. 88

Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults (Abstract)

Jing-Jou Tang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Tsung-Chu Huang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Cheng-Liang Tsai , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 100
Session 2B: Concurrent Error Detection and Fault Tolerance

On Design of Fail-Safe Cellular Arrays (Abstract)

Naotake Kamiura , Himeji Institute of Technology
Kazuharu Yamato , Himeji Institute of Technology
Yutaka Hata , Himeji Institute of Technology
pp. 107

Concurrent Error Detection and Fault Location in a Fast ATM Switch (Abstract)

Yoon-Hwa Choi , Hongik University, Seoul, Korea
Pong-Gyou Lee , Hongik University, Seoul, Korea
pp. 113

Formal Verification Of Self-Testing Properties Of Combinational Circuits (Abstract)

K. Kawakubo , Fac. of Eng., Fukuyama Univ., Japan
H. Hiraishi , Fac. of Eng., Fukuyama Univ., Japan
K. Tanaka , Fac. of Eng., Fukuyama Univ., Japan
pp. 119

Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected Graphs (Abstract)

Yupin Luo , Tsinghua University
Shiyuan Yang , Tsinghua University
Dongcheng Hu , Tsinghua University
pp. 123
Session 3A: Synthesis for Testability

An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan (Abstract)

T. Inoue , Nara Inst. of Sci. & Technol., Japan
T. Masuzawa , Nara Inst. of Sci. & Technol., Japan
H. Youra , Nara Inst. of Sci. & Technol., Japan
H. Fujiwara , Nara Inst. of Sci. & Technol., Japan
pp. 130

Waveform Polynomial Manipulation Using Bdds (Abstract)

Zhuxing Zhao , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Zhongcheng Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 136

Easily Testable Data Path Allocation Using Input/Output Registers (Abstract)

Sy-Yen Kuo , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Jing-Yang Jou , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Li-Ren Huang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Wen-Bin Liao , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 142

AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Tonja Pfeiffer , Johann Wolfgang Goethe-University
Harry Hengster , Albert-Ludwigs-University
Stefan Eckrich , Johann Wolfgang Goethe-University
pp. 148

Minimal Delay Test Sets for Unate Gate Networks (Abstract)

U. Sparmann , University of Saarland
S.M. Reddy , University of Iowa
H. Mueller , University of Saarland
pp. 155
Session 3B: IDDQ and Fault Modeling

Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults (Abstract)

Kuen-Jong Lee , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Jing-Jou Tang , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 165

Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits (Abstract)

Toshimasa Kuchii , The University of Tokushima
Masaki Hashizume , The University of Tokushima
Takeomi Tamesada , The University of Tokushima
pp. 171

An Efficient Compact Test Generator for IDDQ Testing (Abstract)

Kwang-Ting Cheng , University of California, Santa Barbara
Hisashi Kondo , Kawasaki Steel Corp.
pp. 177

Realistic Linked Memory Cell Array Faults (Abstract)

A.J. van de Goor , Delft University of Technology
G.N. Gaydadjiev , Delft University of Technology
pp. 183
Plenary Session: Keynote Speech
Session 4A: Built-In Self-Test

An Efficient PRPG Strategy By Utilizing Essential Faults (Abstract)

Jing-Yang Jou , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Li-Ren Huang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Sy-Yen Kuo , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 199

A MISR Computation Algorithm for Fast Signature Simulation (Abstract)

Bin-Hong Lin , National Tsing Hua University
Shao-Hui Shieh , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
pp. 213
Session 4B: Circuit and System-Level Diagnostics

Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation (Abstract)

Mike W.T. Wong , Hong Kong Polytechnic University
Tao Wei , Hong Kong Polytechnic University
Y.S. Lee , Hong Kong Polytechnic University
pp. 232

A Practical Implementation Of Dynamic Testing Of An Ad Converter (Abstract)

Yuan Tzu Ting , Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan
Wei Chung Chao , Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan
Li Wei Chao , Chung Sun Inst. of Sci. & Technol., Lung-Tan, Taiwan
pp. 238

Comparison Diagnosis in Large Multiprocessor Systems (Abstract)

Christopher P. Fuhrman , Swiss Federal Institute of Technology
Henri J. Nussbaumer , Swiss Federal Institute of Technology
pp. 244
Session 5A: Industrial Applications

Lessons Learned from Practical Applications of BIST/B-S Technology (Abstract)

Najmi Jarwala , Lucent Technologies Bell Labs Innovations
Chi Yau , Lucent Technologies Bell Labs Innovations
Paul W. Rutkowski , Lucent Technologies Bell Labs Innovations
Shianling Wu , Lucent Technologies Bell Labs Innovations
pp. 251

A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology (Abstract)

M. Marzouki , COPPE, Univ. Fed. do Rio de Janeiro, Brazil
A.R. Antunes , COPPE, Univ. Fed. do Rio de Janeiro, Brazil
V.C. Alves , COPPE, Univ. Fed. do Rio de Janeiro, Brazil
pp. 263
Session 5B: Practical Issues

Test Generation Of Analog Switched-Current Circuits (Abstract)

Chin-Long Wey , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Cheng-Ping Wang , Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
pp. 276

Thermal Monitoring Of Safety-Critical Integrated Systems (Abstract)

V. Székely , Technical University of Budapest
J.M Karam , TIMA
M. Rencz , Technical University of Budapest
pp. 282

A New Scheme For The Fault Diagnosis Of Multiprocessor Systems (Abstract)

Hongqing Cao , Comput. Inst., Chongqing Univ., China
Zehan Cao , Comput. Inst., Chongqing Univ., China
Xiaofan Yang , Comput. Inst., Chongqing Univ., China
Zhongshi He , Comput. Inst., Chongqing Univ., China
Tinghuai Chen , Comput. Inst., Chongqing Univ., China
pp. 289

On-Line Testing In Digital Neural Networks (Abstract)

V. Piuri , Singapore Polytech., Singapore
S. Demidenko , Singapore Polytech., Singapore
pp. 295

Author Index (PDF)

pp. 301
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