The Community for Technology Leaders
2012 IEEE 21st Asian Test Symposium (1996)
Hsinchu, TAIWAN
Nov. 20, 1996 to Nov. 22, 1996
ISSN: 1081-7735
ISBN: 0-8186-7478-4
pp: 107
Naotake Kamiura , Himeji Institute of Technology
Kazuharu Yamato , Himeji Institute of Technology
Yutaka Hata , Himeji Institute of Technology
In this paper, we discuss the design of a fail-safe cellular array composed of switch cells. First, we show the design method using a binary decision diagram. Next, we assume stuck-at faults of switch cells to be fault models and discuss the fail-safe property for our array. For all the single faults and part of the multiple faults, our array keeps the fail-safe property. Next, for our arrays realizing randomly generated functions, we derive the ratio of the number of double faults that never break the fail-safe property to the total number of double faults. Finally, in order to demonstrate the advantages of our array, we compare our array with other arrays.
fail-safe logic system, cellular array, Binary Decision Diagram and switch cell
Naotake Kamiura, Kazuharu Yamato, Yutaka Hata, "On Design of Fail-Safe Cellular Arrays", 2012 IEEE 21st Asian Test Symposium, vol. 00, no. , pp. 107, 1996, doi:10.1109/ATS.1996.555145
94 ms
(Ver 3.3 (11022016))