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2012 IEEE 21st Asian Test Symposium (1995)
Bangalore, India
Nov. 23, 1995 to Nov. 24, 1995
ISBN: 0-8186-7129-7
TABLE OF CONTENTS

Program Committee (PDF)

pp. xvii

Reviewers (PDF)

pp. xviii
Session 1 - Systems Test, Chair: D. Nikolos, University of Patras, Greece

Distributed off-line testing of parallel systems (Abstract)

C. Aktouf , Lab. de Genie Inf., IMAG, Grenoble, France
O. Benkahla , Lab. de Genie Inf., IMAG, Grenoble, France
C. Robach , Lab. de Genie Inf., IMAG, Grenoble, France
pp. 2

An SBus Multi-Tracer and its applications (Abstract)

S. Kumar , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
K. Forward , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
H.A. Xie , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
K.M. Adams , Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia
pp. 9

Exploitation of parallelism in group probing for testing massively parallel processing systems (Abstract)

Y.-H. Choi , Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea
C. Kim , Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea
pp. 15

A cellular array designed from a Multiple-valued Decision Diagram and its fault tests (Abstract)

Y. Hata , Fac. of Eng., Himeji Inst. of Technol., Japan
K. Yamato , Fac. of Eng., Himeji Inst. of Technol., Japan
N. Kamiura , Fac. of Eng., Himeji Inst. of Technol., Japan
pp. 20
Session 2 - Analysis Techniques, Chair: S. Xu, Shanghai University of Science and Technology, China

Boolean process-an analytical approach to circuit representation (II) (Abstract)

Yinghua Min , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Zhuxing Zhao , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Zhongcheng Li , Inst. of Comput. Technol., Acad. Sinica, Beijing, China
pp. 26

Fanout fault analysis for digital logic circuits (Abstract)

Wen Zen Shen , Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
J.E. Chen , Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
Beyin Chen , Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
pp. 33

Metastability evaluation method by propagation delay distribution measurement (Abstract)

B. Vojnovic , Ruder Boskovic Inst., Zagreb, Croatia
B.M. Rogina , Ruder Boskovic Inst., Zagreb, Croatia
pp. 40

An approach to hierarchy model checking via evaluating CTL hierarchically (Abstract)

Zuan Zhang , Fraunhofer-Inst. fur Integrierte Schaltungen Erlangen Aussenstelle Dresden, Germany
pp. 45
Session 3 - Diagnosis, Chair: B. Courtois, TZMA, France

Transistor leakage fault location with ZDDQ measurement (Abstract)

H. Tamamoto , Min. Coll., Akita Univ., Japan
K. Kinoshita , Min. Coll., Akita Univ., Japan
Wen Xiaoqing , Min. Coll., Akita Univ., Japan
pp. 51

Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing (Abstract)

Y. Takamatsu , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
N. Yanagida , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
H. Takahashi , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
pp. 58

A simple technique for locating gate-level faults in combinational circuits (Abstract)

E.J. McCluskey , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
K. Yamazaki , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
T. Yamada , Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
pp. 65

A fault location technique and alternate routing in Benes network (Abstract)

N. Das , Electron. Unit, Indian Stat. Inst., Calcutta, India
J. Dattagupta , Electron. Unit, Indian Stat. Inst., Calcutta, India
pp. 71
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan

Overhead reduction techniques for hierarchical fault simulation (Abstract)

E. Harada , ULSI Syst. Dev. Labs., NEC Corp., Kawasaki, Japan
J.H. Patel , ULSI Syst. Dev. Labs., NEC Corp., Kawasaki, Japan
pp. 79

On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation (Abstract)

E.S. Manolakos , Tufts Univ., Medford, MA, USA
E.C. Czeck , Tufts Univ., Medford, MA, USA
K.P. Lentz , Tufts Univ., Medford, MA, USA
pp. 86

Fast fault simulation for BIST applications (Abstract)

Chun-Jieh Huang , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Shang Lin , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chen-Pin Kung , Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 93

Serial transistor network modeling for bridging fault simulation (Abstract)

M. Renovell , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
P. Huc , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 100

Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing (Abstract)

R. Kandlbinder , Fac. of Math. & Comput. Sci., Passau Univ., Germany
A. Hagerer , Fac. of Math. & Comput. Sci., Passau Univ., Germany
W. Hahn , Fac. of Math. & Comput. Sci., Passau Univ., Germany
pp. 107
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India

A design-for-test technique for multistage analog circuits (Abstract)

Y. Bertrand , Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
F. Azais , Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
M. Renovell , Lab. de Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 113

DC control and observation structures for analog circuits (Abstract)

Yeong-Ruey Shieh , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng- Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 120

A new method for testing mixed analog and digital circuits (Abstract)

J. Rzeszut , Ecole Polytech. de Montreal, Que., Canada
B. Kaminska , Ecole Polytech. de Montreal, Que., Canada
Y. Savaria , Ecole Polytech. de Montreal, Que., Canada
pp. 127

On the development of power supply voltage control testing technique for analogue circuits (Abstract)

A.H. Bratt , Microelectron. Res. Group, Lancaster Univ., UK
A.K.B. A'ain , Microelectron. Res. Group, Lancaster Univ., UK
A.P. Dorey , Microelectron. Res. Group, Lancaster Univ., UK
pp. 133

Tolerance DC bands of CMOS operational amplifier (Abstract)

C. Dufaza , Lab. d'Inf., de Robotique et de Micro-electron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
H. Ihs , Lab. d'Inf., de Robotique et de Micro-electron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 140
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan

Theory and applications of cellular automata for synthesis of easily testable combinational logic (Abstract)

P. Pal Chaudhuri , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
S. Nandi , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 146

Unified scan design with scannable memory arrays (Abstract)

S. Yano , 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
pp. 153

Test configurations to enhance the testability of sequential circuits (Abstract)

M. Renovell , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Lavabre , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
Y. Bertrand , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault , Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 160

Test sequence compaction by reduced scan shift and retiming (Abstract)

Y. Higami , Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
S. Kajihara , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 169

Testable design of non-scan sequential circuits using extra logic (Abstract)

D.K. Das , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
B.B. Bhattacharya , Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India
pp. 176
Session 7 - Education and Research in Testing, Chair: V.D. Agrawal, AT&T Bell Labs, USA

Training diploma students on ATE-related module (Abstract)

S.K. Jhajharia , Dept. of Electron. & Commun. Eng., Singapore Polytech., Singapore
H.S. Wang , Dept. of Electron. & Commun. Eng., Singapore Polytech., Singapore
pp. 184
Panel
Session 8 - Testability Measures, Chair: B.B. Bhattacharya, ISI, India

A STAFAN-like functional testability measure for register-level circuits (Abstract)

N. Agrawal , Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
G.S. Saund , Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
C.P. Ravikumar , Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
pp. 192

Testability forecasting for sequential circuits (Abstract)

G.P. Dias , Shanghai Univ. of Sci. & Technol., China
Shiyi Xu , Shanghai Univ. of Sci. & Technol., China
pp. 199

Testability analysis of co-designed systems (Abstract)

Y. Le Traon , LGI-IMAG, Grenoble, France
C. Robach , LGI-IMAG, Grenoble, France
pp. 206
Session 9 - Delay Test I, Chair: P. Varma, CrossCheck, USA

Generator choices for delay test (Abstract)

J. Savir , Power PC Dev. Center, IBM Corp., Austin, TX, USA
pp. 214

Static compaction for two-pattern test sets (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 222

Identification of robust untestable path delay faults (Abstract)

J.E. Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Wen Ching Wu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 229
Session 10 - ATPG, Chair: S. Kundu, IBM, USA

An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits (Abstract)

D.R. Chakrabarti , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
A. Jain , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kanpur, India
pp. 237

Deterministic test generation for non-classical faults on the gate level (Abstract)

U. Mahlstedt , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
I. Hollenbeck , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
J. Alt , Inst. fur Theor. Elektrotech., Hannover Univ., Germany
pp. 244

A parallel sequential test generation system DESCARTES based on real-valued logic simulation (Abstract)

M. Nakao , Res. Lab., Hitachi Ltd., Ibaraki, Japan
H. Date , Res. Lab., Hitachi Ltd., Ibaraki, Japan
K. Hatayama , Res. Lab., Hitachi Ltd., Ibaraki, Japan
pp. 252

Universal test complexity of field-programmable gate arrays (Abstract)

T. Inoue , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
T. Yokohira , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Fujiwara , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
T. Okamoto , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
H. Michinishi , Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
pp. 259

Software transformations for sequential test generation (Abstract)

A. Balakrishnan , RUTCOR, Rutgers Univ., Piscataway, NJ, USA
S.T. Chakradhar , RUTCOR, Rutgers Univ., Piscataway, NJ, USA
pp. 266
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan

Module level weighted random patterns (Abstract)

J. Savir , Power PC Dev. Center, IBM Corp., Austin, TX, USA
pp. 274

A programmable multiple-sequence generator for BIST applications (Abstract)

Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Meng Lieh Sheu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 279

An effective BIST design for PLA (Abstract)

Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 286

Fast computation of C-MISR signatures (Abstract)

M. Franklin , Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
pp. 293

An effective BIST scheme for carry-save and carry-propagate array multipliers (Abstract)

D. Gizopoulos , Inst. of Inf. & Telecommun., Athens, Greece
A. Paschalis , Inst. of Inf. & Telecommun., Athens, Greece
Y. Zorian , Inst. of Inf. & Telecommun., Athens, Greece
pp. 298

Error masking in compact testing based on the Hamming code and its modifications (Abstract)

V. Piuri , Singapore Polytech., Singapore
L. Makhist , Singapore Polytech., Singapore
S. Demidenko , Singapore Polytech., Singapore
A. Ivanyukovich , Singapore Polytech., Singapore
pp. 303
Session 12 - Self-Checking Circuits, Chair: B. Mitra, Texas Instruments, India

An efficient comparative concurrent Built-In Self-Test technique (Abstract)

T. Haniotakis , Inst. of Inf. & Telecommun., Attiki, Greece
I. Voyiatzis , Inst. of Inf. & Telecommun., Attiki, Greece
D. Nikolos , Inst. of Inf. & Telecommun., Attiki, Greece
A. Paschalis , Inst. of Inf. & Telecommun., Attiki, Greece
C. Halatsis , Inst. of Inf. & Telecommun., Attiki, Greece
pp. 309

Totally Self Checking reconfigurable duplication system with separate internal fault indication (Abstract)

N. Gaitanis , Inst. of Inf. & Telecommun., Athens, Greece
P. Kostarakis , Inst. of Inf. & Telecommun., Athens, Greece
A. Paschalis , Inst. of Inf. & Telecommun., Athens, Greece
pp. 316

Generalized modular design of testable m-out-of-n code checker (Abstract)

I. Sen Gupta , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
G. Pada Biswas , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 322

A graph coloring based approach for self-checking logic circuit design (Abstract)

P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
F.Y. Busaba , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 327
Session 13 - Delay Test II, Chair: Y. Min, ICT, China

Generation of tenacious tests for small gate delay faults in combinational circuits (Abstract)

Y. Takamatsu , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
H. Takahashi , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
T. Watanabe , Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
pp. 332

Functional test generation for path delay faults (Abstract)

M.K. Srinivas , CAIP Center, Rutgers Univ., Piscataway, NJ, USA
M.L. Bushnell , CAIP Center, Rutgers Univ., Piscataway, NJ, USA
V.D. Agrawal , CAIP Center, Rutgers Univ., Piscataway, NJ, USA
pp. 339

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits (Abstract)

J.P. Hurst , Center for Digital Syst. Eng., Res. Triangle Inst., Research Triangle Park, NC, USA
N. Kanopoulos , Center for Digital Syst. Eng., Res. Triangle Inst., Research Triangle Park, NC, USA
pp. 346

Sequential logic path delay test generation by symbolic analysis (Abstract)

S. Bose , AT&T Bell Labs., Murray Hill, NJ, USA
V.D. Agrawal , AT&T Bell Labs., Murray Hill, NJ, USA
pp. 353
Session 14 - Technology-Specific Test, Chair: M. Franklin, Clemson University, USA

Low power design and its testability (Abstract)

K. Kinoshita , Dept. of Appl. Phys., Osaka Univ., Japan
H. Ueda , Dept. of Appl. Phys., Osaka Univ., Japan
pp. 361

Power supply current detectability of SRAM defects (Abstract)

Jian Liu , Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
R. Makki , Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
pp. 367
Session 15 - Design-Specific Test, Chair: H. Fujiwara, NAIST, Japan

Fast functional testing of delay-insensitive circuits (Abstract)

S. Pagey , Cadence Design Syst. Ltd., Noida, India
pp. 375

DFT for fast testing of self-timed control circuits (Abstract)

S. Pagey , Cadence Design Syst. Ltd., Noida, India
E. Brunvand , Cadence Design Syst. Ltd., Noida, India
A. Khoche , Cadence Design Syst. Ltd., Noida, India
pp. 382

Testing of a parallel ternary multiplier using I/sup 2/L logic (Abstract)

M. De , USIC, Kalyani Univ., West Bengal, India
B.P. Sinha , USIC, Kalyani Univ., West Bengal, India
pp. 387

Author Index (PDF)

pp. 393
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