2012 IEEE 21st Asian Test Symposium (1995)
Nov. 23, 1995 to Nov. 24, 1995
P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
F.Y. Busaba , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outputs, a minimum set of residue weights are assigned to the output lines so that any error at the outputs can be detected.
graph colouring; graph theory; logic design; logic testing; automatic testing; integrated circuit testing; integrated logic circuits; fault location; error detection; graph coloring; self-checking; logic circuit design; residue codes; single stuck-at fault; bidirectional error; residue weights assignments; output lines; errors identification; error detection
P.K. Lala, F.Y. Busaba, "A graph coloring based approach for self-checking logic circuit design", 2012 IEEE 21st Asian Test Symposium, vol. 00, no. , pp. 327, 1995, doi:10.1109/ATS.1995.485356