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Bangalore, India
Nov. 23, 1995 to Nov. 24, 1995
ISBN: 0-8186-7129-7
pp: 327
F.Y. Busaba , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
P.K. Lala , Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outputs, a minimum set of residue weights are assigned to the output lines so that any error at the outputs can be detected.
graph colouring; graph theory; logic design; logic testing; automatic testing; integrated circuit testing; integrated logic circuits; fault location; error detection; graph coloring; self-checking; logic circuit design; residue codes; single stuck-at fault; bidirectional error; residue weights assignments; output lines; errors identification; error detection
F.Y. Busaba, P.K. Lala, "A graph coloring based approach for self-checking logic circuit design", ATS, 1995, 2012 IEEE 21st Asian Test Symposium, 2012 IEEE 21st Asian Test Symposium 1995, pp. 327, doi:10.1109/ATS.1995.485356
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