2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) (2015)
Mountain View, CA, USA
May 4, 2015 to May 6, 2015
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2015.19
Asynchrony and concurrency are fundamental notions in the fields of asynchronous circuits as well as distributed systems. This paper treats asynchronous circuits as a special class of distributed systems. We adapt the distributed systems notion of potential causality to asynchronous circuits, and use it to provide a formal proof of the precise nature of the isochronic fork timing assumption in quasi delay-insensitive (QDI) circuits. Our proofs provide a transparent analysis that provides better intuition regarding the operation of QDI circuits. We build on our theory to rigorously establish several "folk theorems" about identifying isochronic forks in QDI circuits.
Logic gates, Wires, Asynchronous circuits, Delays, Integrated circuit modeling,
Rajit Manohar, Yoram Moses, "Analyzing Isochronic Forks with Potential Causality", 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), vol. 00, no. , pp. 69-76, 2015, doi:10.1109/ASYNC.2015.19