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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2012)
Lyngby Denmark
May 7, 2012 to May 9, 2012
ISSN: 1522-8681
ISBN: 978-0-7695-4688-9
pp: 65-72
Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used to produce a gate-level net list of primitive logic gates and storage elements, which is then transformed into an NCL net list by the Uncle mapping flow. Performance optimizations supported by the flow are net buffering for target slew and delay balancing between latch stages. Both data-driven and control-driven (i.e. Balsa-style) schemes are supported. Transistor count, performance, and energy comparisons are made for Uncle versus Balsa-generated net lists for GCD and Viterbi decoder designs, with the Uncle designs comparing favorably in all three areas.
RTL, asynchronous, NULL Convention Logic, synthesis

"Uncle - An RTL Approach to Asynchronous Design," 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems(ASYNC), Lyngby Denmark, 2012, pp. 65-72.
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