The Community for Technology Leaders
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2007)
Berkeley, California
Mar. 12, 2007 to Mar. 14, 2007
ISSN: 1522-8681
ISBN: 0-7695-2771-X
TABLE OF CONTENTS
Introduction

Committees (PDF)

pp. x
Invited Talk 1
Invited Talk 2
Invited Talk 3
Invited Talk 4
Session 1: High-Speed Links and Signaling

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link (Abstract)

Avinoam Kolodny , Israel Institute of Technology, Haifa
Yevgeny Perelman , Israel Institute of Technology, Haifa
Rostislav Reuven Dobkin , Israel Institute of Technology, Haifa
Ran Ginosar , Israel Institute of Technology, Haifa
Tuvia Liran , Israel Institute of Technology, Haifa
pp. 3-14

Notes On Pulse Signaling (Abstract)

Arash Saifhashemi , Sun Microsystems Laboratories, Menlo Park
Steve Furber , Sun Microsystems Laboratories, Menlo Park
Jo Ebergen , Sun Microsystems Laboratories, Menlo Park
pp. 15-24

A Jitter Attenuating Timing Chain (Abstract)

Jihong Ren , Intel
Suwen Yang , SUN Microsystems, and NSERC
Mark R. Greenstreet , SUN Microsystems, and NSERC
pp. 25-38
Session 2: Asynchronous Applications

The Vortex: A Superscalar Asynchronous Processor (Abstract)

Andrew Lines , Fulcrum Microsystems, Calabasas, CA, USA
pp. 39-48

Design of a High-Speed Asynchronous Turbo Decoder (Abstract)

Georgios D. Dimou , University of Southern California, Los Angeles
Mallika Prakash , University of Southern California, Los Angeles
Peter A. Beerel , University of Southern California, Los Angeles
Pankaj Golani , University of Southern California, Los Angeles
pp. 49-59

Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus (Abstract)

John Bainbridge , Silistix Ltd., Manchester, UK
Andrew M. Scott , Intel Corporation, Austin, TX
Marly Roncken , Intel Corporation, Austin, TX
Mark E. Schuelein , Intel Corporation, Austin, TX
Andrew Bardsley , Silistix Ltd., Manchester, UK
John R. Mawer , Silistix Ltd., Manchester, UK
Jin-Jer Hwan , Intel Corporation, Austin, TX
David L. Jackson , Silistix Ltd., Manchester, UK
pp. 60-72
Session 3: Verification

Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip (Abstract)

Gwen Salaun , INRIA Rhone-Alpes / VASY, Montbonnot, France
Yvain Thonnart , CEA/Leti - MINATEC, Grenoble, France
Pascal Vivet , CEA/Leti - MINATEC, Grenoble, France
Wendelin Serwe , INRIA Rhone-Alpes / VASY, Montbonnot, France
pp. 73-82
Session 4: Novel Circuits

The Design of a Genetic Muller C-Element (Abstract)

James P. Keener , University of Utah
Hiroyuki Kuwahara , University of Utah
Nam-Phuong D. Nguyen , University of Utah
Chris J. Myers , University of Utah
pp. 95-104

Delay/Phase Regeneration Circuits (Abstract)

Alex Yakovlev , Newcastle University, UK
Alex Bystrov , Newcastle University, UK
Crescenzo D?Alessandro , Newcastle University, UK
Andrey Mokhov , Newcastle University, UK
pp. 105-116
Session 5: Synthesis

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis (Abstract)

Tiberiu Chelcea , Carnegie Mellon University
Girish Venkataramani , Carnegie Mellon University
Seth C. Goldstein , Carnegie Mellon University
pp. 117-128
Session 6: Test and Measurement

A Configurable Asynchronous Pseudorandom Bit Sequence Generator (Abstract)

William S. Coates , Sun Microsystems, Menlo Park, CA
David Hopkins , Sun Microsystems, Menlo Park, CA
Alex Chow , Sun Microsystems, Menlo Park, CA
pp. 143-152

On-chip samplers for test and debug of asynchronous circuits (Abstract)

Robert Drost , Sun Microsystems Laboratories, Menlo Park, CA
Scott Fairbanks , Sun Microsystems Laboratories, Menlo Park, CA
Ron Ho , Sun Microsystems Laboratories, Menlo Park, CA
Frankie Liu , Sun Microsystems Laboratories, Menlo Park, CA
pp. 153-162

A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability (Abstract)

Nikolaos Minas , Newcastle University, UK
Keith Heron , Newcastle University, UK
David Kinniment , Newcastle University, UK
Gordon Russell , Newcastle University, UK
pp. 163-174
Session 7: Interfaces

Demystifying Data-Driven and Pausible Clocking Schemes (Abstract)

Robert Mullins , University of Cambridge, UK
Simon Moore , University of Cambridge, UK
pp. 175-185

Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication (Abstract)

Steven M. Nowick , Columbia University
William F. McLaughlin , Columbia University
Amitava Mitra , Intel Corporation, Bangalore, India
pp. 186-195
Author Index

Author Index (PDF)

pp. 205
105 ms
(Ver )