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13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) (2007)
Berkeley, California
Mar. 12, 2007 to Mar. 14, 2007
ISSN: 1522-8681
ISBN: 0-7695-2771-X
pp: 73-82
Gwen Salaun , INRIA Rhone-Alpes / VASY, Montbonnot, France
Wendelin Serwe , INRIA Rhone-Alpes / VASY, Montbonnot, France
Yvain Thonnart , CEA/Leti - MINATEC, Grenoble, France
Pascal Vivet , CEA/Leti - MINATEC, Grenoble, France
ABSTRACT
<p>Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architectures described in the high-level language CHP, by using model checking techniques provided by the CADP toolbox. Our proposal is based on an automatic translation from CHP into LOTOS, the process algebra used in CADP. A translator has been implemented, which handles full CHP including the specific probe operator.</p> <p>The CADP toolbox capabilities allow the designer to verify properties such as deadlock-freedom or protocol correctness on substantial systems. Our approach has been successfully applied to formally verify two complex designs. In this paper, we illustrate our technique on an asynchronous Network-on-Chip architecture. Its formal verification highlights the need to carefully design systems exhibiting nondeterministic behavior.</p>
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CITATION

G. Salaun, Y. Thonnart, P. Vivet and W. Serwe, "Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip," 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)(ASYNC), Berkeley, California, 2007, pp. 73-82.
doi:10.1109/ASYNC.2007.18
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