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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2006)
Grenoble, France
Mar. 13, 2006 to Mar. 15, 2006
ISSN: 1522-8681
ISBN: 0-7695-2498-2
TABLE OF CONTENTS
Introduction

Message from the Chairs (PDF)

pp. viii-viiii
Cover
Introduction

Committees (PDF)

pp. x
Invited Talk 1
Session 1: Interfacing and Synchronization

Measuring Deep Metastability (Abstract)

David Kinniment , Newcastle University, UK
Gordon Russell , Newcastle University, UK
Keith Heron , Newcastle University, UK
pp. 2-11

A Level-Crossing Flash Asynchronous Analog-to-Digital Converter (Abstract)

Rajit Manohar , Cornell University
Filipp Akopyan , Cornell University
Alyssa B. Apsel , Cornell University
pp. 12-22

An Asynchronous High-Throughput Control Circuit For Proximity Communication (Abstract)

David Hopkins , Sun Microsystems Laboratories, USA
Bill Coates , Sun Microsystems Laboratories, USA
Justin Schauer , Sun Microsystems Laboratories, USA
Alex Chow , Sun Microsystems Laboratories, USA
Jo Ebergen , Sun Microsystems Laboratories, USA
pp. 23-33
Session 2: Fault-Tolerance and Testing

Self-Healing Asynchronous Arrays (Abstract)

Song Peng , Cornell University
Rajit Manohar , Cornell University
pp. 34-45

Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines (Abstract)

Feng Shi , Yale University
Gennette Gill , UNC Chapel Hill
Ankur Agiwal , UNC Chapel Hill
Montek Singh , UNC Chapel Hill
Yiorgos Makris , Yale University
pp. 46-56
Session 3: Novel Architectures and Design Practices

An ultra-low energy asynchronous processor for Wireless Sensor Networks (Abstract)

L. Necchi , Politecnico di Torino, Italy
L. Lavagno , Politecnico di Torino, Italy
D. Pandini , STMicroelectronics Agrate (MI), Italy
L. Vanzago , STMicroelectronics Agrate (MI), Italy
pp. 78-85

AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation (Abstract)

D. Caucheteux , CEA-Grenoble, LETI-DCIS, Cedex, France
E. Beigne , CEA-Grenoble, LETI-DCIS, Cedex, France
E. Crochon , CEA-Grenoble, LETI-DCIS, Cedex, France
M. Renaudin , TIMA Laboratory, CIS Group, Cedex, France
pp. 86-97
Invited Talk 2
Session 4: Interconnect and Communcations

Surfing Interconnect (Abstract)

Jihong Ren , University of British Columbia
Mark R. Greenstreet , University of British Columbia
pp. 98-106

Multiple-Rail Phase-Encoding for NoC (Abstract)

Alex Bystrov , University of Newcastle upon Tyne, UK
Oleg Maevsky , Intel Labs, Moscow, RU
Alex Yakovlev , University of Newcastle upon Tyne, UK
Crescenzo D?Alessandro , University of Newcastle upon Tyne, UK
Delong Shang , University of Newcastle upon Tyne, UK
pp. 107-116

Fast Asynchronous Shift Register for Bit-Serial Communication (Abstract)

Rostislav (Reuven) Dobkin , Israel Institute of Technology, Haifa, Israel
Avinoam Kolodny , Israel Institute of Technology, Haifa, Israel
Ran Ginosar , Israel Institute of Technology, Haifa, Israel
pp. 117-127
Session 5: Synthesis

Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks (Abstract)

Cheoljoo Jeong , Columbia University, NY
Steven M. Nowick , Columbia University, NY
pp. 128-137

Synthesising Heterogeneously Encoded Systems (Abstract)

D. A. Edwards , University of Manchester, UK
W. B. Toms , University of Manchester, UK
A Bardsley , Silistix Ltd., UK
pp. 138-149
Invited Talk 3

Asynchronous Architectures for Nanometer Scales (PDF)

Ferdinand Peper , National Institute of Information and Communications Technology, Japan
pp. xiv
Session 6: Design and Architectures for GALS

GALS at ETH Zurich: Success or Failure (Abstract)

Wolfgang Fichtner , Integrated Systems Laboratory, CH-8092 ETH Zurich
Norbert Felber , Integrated Systems Laboratory, CH-8092 ETH Zurich
Hubert Kaeslin , Integrated Systems Laboratory, CH-8092 ETH Zurich
Stephan Oetiker , Integrated Systems Laboratory, CH-8092 ETH Zurich
Frank K. Gurkaynak , Integrated Systems Laboratory, CH-8092 ETH Zurich
pp. 150-159

Interface Design for Rationally Clocked GALS Systems (Abstract)

Supratik Chakraborty , Indian Institute of Technology, Bombay
P. S. Thiagarajan , National University of Singapore
D.K. Sharma , Indian Institute of Technology, Bombay
Joycee Mekie , Indian Institute of Technology, Bombay
Girish Venkataramani , Carnegie Mellon University
pp. 160-171

Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture (Abstract)

E. Beigne , CEA-LETI, France
P. Vivet , CEA-LETI, France
pp. 172-183
Session 7: Slack Matching

Slack Matching Asynchronous Designs (Abstract)

Andrew Lines , Fulcrum Microsystems, Inc., Calabasas Hills, CA
Mike Davies , Fulcrum Microsystems, Inc., Calabasas Hills, CA
Peter A. Beerel , University of Southern California
Nam-Hoon Kim , University of Southern California
pp. 184-194

Slack Matching Quasi Delay-Insensitive Circuits (Abstract)

Piyush Prakash , California Institute of Technology
Alain J. Martin , California Institute of Technology
pp. 195-204
Author Index

Author Index (PDF)

pp. 205
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