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11th IEEE International Symposium on Asynchronous Circuits and Systems (2005)
New York City, New York, USA
Mar. 14, 2005 to Mar. 16, 2005
ISSN: 1522-8681
ISBN: 0-7695-2305-6
Invited Talk 1

Deep Pipelines vs. Risk and Power Walls (PDF)

Bob Colwell , R.E. Collwell and Associates, Inc.
pp. xi
Session 1: Circuit Techniques

null (PDF)

pp. null

Energy Efficient Surfing (Abstract)

Suwen Yang , University of British Columbia
Brian D. Winters , University of British Columbia
Mark R. Greenstreet , University of British Columbia
pp. 2-11

GasP Control for Domino Circuits (Abstract)

Jo Ebergen , Sun Microsystems Laboratories
Jonathan Gainsley , Sun Microsystems Laboratories
Jon Lexau , Sun Microsystems Laboratories
Ivan Sutherland , Sun Microsystems Laboratories
pp. 12-22
Session 2: On-Chip Networks

null (PDF)

pp. null

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip (Abstract)

Tobias Bjerregaard , Technical University of Denmark
Jens Spars? , Technical University of Denmark
pp. 34-43

An Asynchronous Router for Multiple Service Levels Networks on Chip (Abstract)

Dobkin (Reuven) Rostislav , Technion-Israel Institute of Technology
Victoria Vishnyakov , Technion-Israel Institute of Technology
Eyal Friedman , Technion-Israel Institute of Technology
Ran Ginosar , Technion-Israel Institute of Technology
pp. 44-53
Session 3: Clocking and Synchronization

null (PDF)

pp. null

Register Communication between Mutually Asynchronous Domains (Abstract)

Joep Kessels , Philips Technology Incubator
pp. 66-75

Self-Timed Circuitry for Global Clocking (Abstract)

Scott Fairbanks , Cambridge University
Simon Moore , Cambridge University
pp. 86-96
Invited Talk 2

Proximity Communication and Time (PDF)

Robert Drost , Sun Microsystems Laboratories
Ivan Sutherland , Sun Microsystems Laboratories
pp. xii
Session 4: Design Analysis

null (PDF)

pp. null

Modeling and Verifying Circuits Using Generalized Relative Timing (Abstract)

Sanjit A. Seshia , Carnegie Mellon University
Randal E. Bryant , Carnegie Mellon University
Kenneth S. Stevens , Intel Strategic CAD Labs
pp. 98-108

Delay Insensitive Encoding and Power Analysis: A Balancing Act (Abstract)

Konrad J. Kulikowski , Boston University
Ming Su , Boston University
Alexander Smirnov , Boston University
Alexander Taubin , Boston University
Mark G. Karpovsky , Boston University
Daniel MacDonald , Boston University
pp. 116-125
Session 5: Design Implementations

null (PDF)

pp. null

A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier (Abstract)

Justin Hensley , University of North Carolina
Anselmo Lastra , University of North Carolina
Montek Singh , University of North Carolina
pp. 128-137

Continuous-Time Digital Signal Processors (Abstract)

Y. W. Li , Columbia University
K. L. Shepard , Columbia University
Y. P. Tsividis , Columbia University
pp. 138-143
Session 6: Test and Reliability

null (PDF)

pp. null

SEU-Tolerant QDI Circuits (Abstract)

Wonjin Jang , California Institute of Technology
Alain Martin , California Institute of Technology
pp. 156-165

A Multiplexor Based Test Method for Self-Timed Circuits (Abstract)

Frank te Beest , Philips Technology Incubator
Ad Peeters , Philips Technology Incubator
pp. 166-175
Invited Tutorial
Session 7: Encoding and Synthesis

null (PDF)

pp. null

High Level Synthesis of Timed Asynchronous Circuits (Abstract)

Tomohiro Yoneda , National Institute of Informatics
Atsushi Matsumoto , Tokyo Institute of Technology
Manabu Kato , Tokyo Institute of Technology
Chris Myers , University of Utah
pp. 178-189

Behavior and Synthesis of Two-Input Gate Asynchronous Circuits (Abstract)

Nikolai Starodoubtsev , Tokyo University of Social Welfare
Sergei Bystrov , Russian Academy of Science
pp. 190-200

A Unified Coding Framework for Delay-Insensitivity (Abstract)

Frédéric Worm , Ecole Polytechnique Fédérale de Lausanne
Patrick Thiran , Ecole Polytechnique Fédérale de Lausanne
Paolo Ienne , Ecole Polytechnique Fédérale de Lausanne
pp. 201-211
Author Index

Author Index (PDF)

pp. 212
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