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10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings. (2004)
Crete, Greece
Apr. 19, 2004 to Apr. 23, 2004
ISSN: 1522-8681
ISBN: 0-7695-2133-9
pp: 159-169
Greg Semeraro , Rochester Institute of Technology
David H. Albonesi , University of Rochester
Grigorios Magklis , University of Rochester
Michael L. Scott , University of Rochester
Steven G. Dropsho , University of Rochester
Sandhya Dwarkadas , University of Rochester
ABSTRACT
We analyze an Alpha 21264-like Globally-Asynchronous, Locally-Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of the processor that influence the limited performance degradation measured. We show that the out-of-order superscalar execution features of a processor, which allow traditional instruction execution latency to be hidden, are the same features that reduce the performance degradation impact of the synchronization costs of an MCD processor. In the case of our Alpha 21264-like processor, up to 94% of the MCD synchronization delays are hidden and do not impact overall performance. In addition, we show that by adding out-of-order superscalar execution capabilities to a simpler michroarchitecture, such as an Intel StrongARM-like processor, as much as 62% of the performance degradation caused by synchronization delays can be elimidated.
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CITATION

S. Dwarkadas, D. H. Albonesi, G. Magklis, G. Semeraro, S. G. Dropsho and M. L. Scott, "Hiding Synchronization Delays in a GALS Processor Microarchitecture," 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings.(ASYNC), Crete, Greece, 2004, pp. 159-169.
doi:10.1109/ASYNC.2004.1299297
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