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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2003)
Vancouver, B.C., Canada
May 12, 2003 to May 15, 2003
ISSN: 1522-8681
ISBN: 0-7695-1898-2
TABLE OF CONTENTS
Introduction
Keynote I
Session I: Asynchronous Processors

A Coarse-Grain Phased Logic CPU (Abstract)

Robert B. Reese , Mississippi State University
Cherrice Traver , Union College
Mitchell A. Thornton , Southern Methodist University
pp. 2

The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller (Abstract)

Alain J. Martin , California Institute of Technology
Piyush Prakash , California Institute of Technology
Eino-Ville Talvala , California Institute of Technology
Kevin S. Ko , California Institute of Technology
Mika Nyström , California Institute of Technology
Jonathan Chang , California Institute of Technology
Benjamin Lee , California Institute of Technology
James Pugh , California Institute of Technology
Elaine Ou , California Institute of Technology
Catherine G. Wong , California Institute of Technology
Ahmet Tura , California Institute of Technology
James T. Tong , California Institute of Technology
Karl Papadantonakis , California Institute of Technology
Paul I. Pénzes , California Institute of Technology
pp. 14

SNAP: A Sensor-Network Asynchronous Processor (Abstract)

Rajit Manohar , Cornell University
Clinton Kelly, IV , Cornell University
Virantha Ekanayake , Cornell University
pp. 24
Session II: Pipeline Design and Tools

Congestion and Starvation Detection in Ripple FIFOs (Abstract)

William S. Coates , Sun Microsystems, Inc.
Robert J. Drost , Sun Microsystems, Inc.
pp. 36

Adaptive Pipeline Structures fo Speculation Control (Abstract)

Jim D. Garside , University of Manchester
Aristides Efthymiou , University of Manchester
pp. 46
Session III: Synchronization

Timing Measurements of Synchronization Circuits (Abstract)

Ran Ginosar , Israel Institute of Technology
Yaron Semiat , Israel Institute of Technology
pp. 68

Efficient Self-Timed Interfaces for Crossing Clock Domains (Abstract)

Mark R. Greenstreet , University of British Columbia
Ajanta Chakraborty , University of British Columbia
pp. 78

Fourteen Ways to Fool Your Synchronizer (Abstract)

Ran Ginosar , Israel Institute of Technology
pp. 89
Keynote II
Session IV: Asynchronous Circuit Analysis

Monotonic Circuits with Complete Acknowledgement (Abstract)

Alex Yakovlev , University of Newcastle upon Tyne
Sergei Bystrov , Russian Academy of Science
Nikolai Starodoubtsev , Tokyo University of Social Welfare
pp. 98

On the Existence of Hazard-Free Multi-Level Logic (Abstract)

Charles W. O ?Donnell , Columbia University
Steven M. Nowick , Columbia University
pp. 109
Session V: Interconnect Methods

Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes (Abstract)

W. J. Bainbridge , University of Manchester
S. B. Furber , University of Manchester
W. B. Toms , University of Manchester
D. A. Edwards , University of Manchester
pp. 132

Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems (Abstract)

Wolfgang Fichtner , Swiss Federal Institute of Technology
Thomas Villiger , Swiss Federal Institute of Technology
Frank K. G?rkaynak , Swiss Federal Institute of Technology
Hubert K?slin , Swiss Federal Institute of Technology
Stephan Oetiker , Swiss Federal Institute of Technology
pp. 141

A High-Speed Clockless Serial Link Transceiver (Abstract)

John Teifel , Cornell University
Rajit Manohar , Cornell University
pp. 151
Keynote III
Session VI: Synthesis

Low-Latency Contro Structures with Slack (Abstract)

D. Sokolov , University of Newcastle upon Tyne
A. Bystrov , University of Newcastle upon Tyne
A. Yakovlev , University of Newcastle upon Tyne
pp. 164

Asynchronous DRAM Design and Synthesis (Abstract)

Virantha N. Ekanayak , Cornell University
Rajit Manohar , Cornell University
pp. 174

Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions (Abstract)

Hiroshi Nakamura , University of Tokyo
Euiseok Kim , University of Tokyo
Takashi Nanya , University of Tokyo
Nattha Sretasereekul , University of Tokyo
Hiroshi Saito , University of Tokyo
Masashi Imai , University of Tokyo
pp. 184
Session VII: Power Management in Security and Signal Processing

A New Class of Asynchronous A/D Converters Based on Time Quantization (Abstract)

L. Fesquet , TIMA Laboratory
E. Allier , TIMA Laboratory
G. Sicard , TIMA Laboratory
M. Renaudin , TIMA Laboratory
pp. 196

An Investigation into the Security of Self-Timed Circuits (Abstract)

S. B. Furber , University of Manchester
L. A. Plana , University of Manchester
Z. C. Yu , University of Manchester
pp. 206

Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Applications (Abstract)

George Patounakis , Columbia University
S. M. Nowick , Columbia University
Anup Jose , Columbia University
K. L. Shepard , Columbia University
Yee William Li , Columbia University
pp. 216
Keynote IV
Author Index

Author Index (PDF)

pp. 227
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