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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2003)
Vancouver, B.C., Canada
May 12, 2003 to May 15, 2003
ISSN: 1522-8681
ISBN: 0-7695-1898-2
pp: 132
W. J. Bainbridge , University of Manchester
S. B. Furber , University of Manchester
W. B. Toms , University of Manchester
D. A. Edwards , University of Manchester
ABSTRACT
<p>m-of-n codes can be used for carrying data over self-timed on-chip interconnect links. Such codes can be chosen to have low redundancy, but the costs of encoding/decoding data is high. The key to enabling the cost-effective use of m-of-n codes is to find a suitable mapping of the binary data to the code.</p> <p>This paper presents a new method for selecting suitable mappings through the decomposition of the complex m-of-n code into an incomplete m-of-n code constructed from groups of smaller, simpler m-of-n and 1-of-n codes.</p> <p>The circuits used both for completion detection and for encoding/decoding such incomplete codes show reduced logic size and delay compared to their full m-of-n counter-parts. The improvements mean that the incomplete m-of-n codes become attractive for use in on-chip interconnects and network-on-chip designs.</p>
INDEX TERMS
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CITATION
W. J. Bainbridge, S. B. Furber, W. B. Toms, D. A. Edwards, "Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes", 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, vol. 00, no. , pp. 132, 2003, doi:10.1109/ASYNC.2003.1199173
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