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Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings. (2003)
Vancouver, B.C., Canada
May 12, 2003 to May 15, 2003
ISSN: 1522-8681
ISBN: 0-7695-1898-2
pp: 2
Robert B. Reese , Mississippi State University
Mitchell A. Thornton , Southern Methodist University
Cherrice Traver , Union College
ABSTRACT
A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed implementation scheme known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of PL blocks. Each PL block is composed of control logic wrapped around a collection of DFFs and LUT4s to form a multi-input/output PL gate. PL offers a speedup technique known as early evaluation that can be used to boost performance at the cost of additional logic within each block. In addition to early evaluation, this implementation uses bypass paths in the ALU for shift and logical instructions and buffering stages for increased dataflow to further improve performance. Additional speedup is gained by reordering instructions to provide more opportunity for early evaluation. Simulation results show an average speedup of 41% compared to the clocked netlist over a suite of five benchmark programs.
INDEX TERMS
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CITATION

R. B. Reese, C. Traver and M. A. Thornton, "A Coarse-Grain Phased Logic CPU," Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.(ASYNC), Vancouver, B.C., Canada, 2003, pp. 2.
doi:10.1109/ASYNC.2003.1199161
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