Energy-efficient pipelines (PDF)
Clock synchronization through handshake signalling (PDF)
Asynchronous circuit synthesis by direct mapping: interfacing to environment (PDF)
Design and performance analysis of buffers: a constructive approach (PDF)
Message from the Chairs (PDF)
Symposium Committee (PDF)
A functional test methodology for globally-asynchronous locally-synchronous systems (PDF)
On-chip structures for timing measurement and test (PDF)
SPA - a synthesisable Amulet core for smartcard applications (PDF)
High-Speed QDI Asynchronous Pipelines (Abstract)
Energy-Efficient Pipelines (Abstract)
A Negative-Overhead, Self-Timed Pipeline (Abstract)
An Event Spacing Experiment (Abstract)
Clock Synchronization through Handshake Signalling (Abstract)
Point to Point GALS Interconnect (Abstract)
A Dual-Mode Synchronous/Asynchronous CORDIC Processor (Abstract)
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays (Abstract)
Relative Timing Based Verification of Timed Circuits and Systems (Abstract)
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment (Abstract)
Design and Performance Analysis of Buffers: A Constructive Approach (Abstract)
Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond (Abstract)
Adding Synchronous and LSSD Modes to Asynchronous Circuits (Abstract)
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach (Abstract)
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems (Abstract)
On-Chip Structures for Timing Measurements and Test (Abstract)
SPA — A Synthesisable Amulet Core for Smartcard pplications (Abstract)
Improving Smart Card Security Using Self-Timed Circuits (Abstract)
Taking Asynchronous Design to the Market (PDF)
Author Index (PDF)