CSDL - Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC

Proceedings Eighth International Symposium on Asynchronous Circuits and Systems (2002)

Manchester, United Kingdom

Apr. 8, 2002 to Apr. 11, 2002

ISSN: 1522-8681

ISBN: 0-7695-1540-1

TABLE OF CONTENTS

Proceedings Eighth International Symposium on Asynchronous Circuits and Systems (PDF)

pp.

Energy-efficient pipelines (PDF)

J. Teifel , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

D. Fang , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

D. Biermann , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

C. Kelly , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

R. Manohar , Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

pp. 23-33

Clock synchronization through handshake signalling (PDF)

J. Kessels , Philips Res. Lab., Eindhoven, Netherlands

A. Peeters , Philips Res. Lab., Eindhoven, Netherlands

P. Wielage , Philips Res. Lab., Eindhoven, Netherlands

Suk-Jin Kim

pp. 59-68

Asynchronous circuit synthesis by direct mapping: interfacing to environment (PDF)

A. Bystrov , Newcastle upon Tyne Univ., UK

A. Yakovlev , Newcastle upon Tyne Univ., UK

pp. 127-136

Design and performance analysis of buffers: a constructive approach (PDF)

R.H. Mak , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands

pp. 137-148

Checking delay-insensitivity: 10/sup 4/ gates and beyond (PDF)

pp. 149-157

Message from the Chairs (PDF)

pp. vii

Symposium Committee (PDF)

pp. ix

Steering Committee (PDF)

pp. x

Technical Programme Committee (PDF)

pp. xi

Paper Session 1: High-Speed and Energy-Efficient Pipelines - Chair: Jim Garside

Synchronous Interlocked Pipelines (Abstract)

Hans M. Jacobson , IBM T.J. Watson Research Center

Prabhakar N. Kudva , IBM T.J. Watson Research Center

Pradip Bose , IBM T.J. Watson Research Center

Peter W. Cook , IBM T.J. Watson Research Center

Stanley E. Schuster , IBM T.J. Watson Research Center

pp. 3

High-Speed QDI Asynchronous Pipelines (Abstract)

Peter A. Beerel , University of Southern California

Recep O. Ozdag , University of Southern California

pp. 13

Energy-Efficient Pipelines (Abstract)

John Teifel , Cornell University

Clint Kelly , Cornell University

David Fang , Cornell University

Rajit Manohar , Cornell University

David Biermann , Cornell University

pp. 23

Paper Session 2: Novel Self-Timed Circuit Experiments - Chair: Ivan Sutherland

A Negative-Overhead, Self-Timed Pipeline (Abstract)

Mark R. Greenstreet , University of British Columbia

Brian D. Winters , University of British Columbia

pp. 37

An Event Spacing Experiment (Abstract)

Aurelien Garivier , L'Ecole Normale Superieure

Anthony Winstanley , University of British Columbia

Mark Greenstreet , University of British Columbia

pp. 47

Keynote Session I - Chair: Steve Furber

How the ARM Architecture Moved from a Start-Up Idea in Acorn Computers to Become a Global Standard (PDF)

Robin Saxby , ARM Ltd.

pp. null

Paper Session 3: Mixed Synchronous/Asynchronous Communication and Design

Clock Synchronization through Handshake Signalling (Abstract)

Joep Kessels , Philips Research

Suk-Jin Kim , Kwang-Ju Institute of Science and Technology

Ad Peeters , Philips Research

Paul Wielage , Philips Research

pp. 59

Point to Point GALS Interconnect (Abstract)

Robert Mullins , University of Cambridge

Peter Robinson , University of Cambridge

Simon Moore , University of Cambridge

George Taylor , University of Cambridge

pp. 69

A Dual-Mode Synchronous/Asynchronous CORDIC Processor (Abstract)

Eckhard Grass , IHP

Koushik Maharatna , IHP

Bodhisatya Sarker , IHP

pp. 76

An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz (Abstract)

Steven M. Nowick , Columbia University

Montek Singh , University of North Carolina at Chapel Hill

Sergey Rylov , IBM Thomas J. Watson Research Center

Alexander Rylyakov , IBM Thomas J. Watson Research Center

Jose A. Tierno , IBM Thomas J. Watson Research Center

pp. 84

Keynote Session II - Chair: Peter Robinson

Nanomagnetic Logic Devices (PDF)

Russell Cowburn , University of Durham

pp. null

Paper Session 4: Timing Analysis and Verification - Chair: Mark Josephs

Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays (Abstract)

Rohan Angrish , Stanford University

Supratik Chakraborty , Indian Institute of Technology, Bombay

pp. 99

Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits (Abstract)

Metehan Özcan , University of Tokyo

Takashi Nanya , University of Tokyo

Masashi Imai , University of Tokyo

pp. 109

Relative Timing Based Verification of Timed Circuits and Systems (Abstract)

Ken Stevens , Intel Corporation

Peter A. Beerel , University of Southern California

Hoshik Kim , University of Southern California

pp. 115

Paper Session 5: High-Level Design and Analysis of Self-Timed Circuits - Luciano Lavagno

Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment (Abstract)

Alex Yakovlev , University of Newcastle upon Tyne

Alexandre Bystrov , University of Newcastle upon Tyne

pp. 127

Design and Performance Analysis of Buffers: A Constructive Approach (Abstract)

Rudolf H. Mak , Technische Universiteit Eindhoven

pp. 137

Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond (Abstract)

Lawrence Neukom , Verific Design Automation

Alexander Taubin , Boston University

Alex Kondratyev , Cadence Berkeley Laboratories

Oriol Roig , Cadence Berkeley Laboratories

Karl Fant , Theseus Research

pp. 149

Keynote Session III

Mobile Applications (PDF)

Nick Foggin , Orange

pp. null

Paper Session 6: Production Testing - Chair: Marly Roncken

Adding Synchronous and LSSD Modes to Asynchronous Circuits (Abstract)

Ad Peeters , Philips Research Laboratories

Frank de Beest , University of Twente

Kees van Berkel , Philips Research Laboratories and Eindhoven University of Technology

pp. 161

Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach (Abstract)

Alex Kondratyev , Cadence Berkeley Laboratory

Amy Streich , Theseus Logic, Inc.

Lief Sorensen , Theseus Logic, Inc.

pp. 171

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems (Abstract)

S. Oetiker , Swiss Federal Institute for Technology

H. Kaeslin , Swiss Federal Institute for Technology

T. Villiger , Swiss Federal Institute for Technology

W. Fichtner , Swiss Federal Institute for Technology

N. Felber , Swiss Federal Institute for Technology

F. Gürkaynak , Swiss Federal Institute for Technology

pp. 181

On-Chip Structures for Timing Measurements and Test (Abstract)

D. J. Kinniment , Newcastle University

G. Russell , Newcastle University

A. Bystrov , Newcastle University

O. V. Maevsky , Newcastle University

A. V. Yakovlev , Newcastle University

pp. 190

Paper Session 7: Security - Chair: Joep Kessels

SPA — A Synthesisable Amulet Core for Smartcard pplications (Abstract)

A. Bardsley , University of Manchester

J. D. Garside , University of Manchester

P. A. Riocreux , University of Manchester

L. A. Plana , University of Manchester

W. J. Bainbridge , University of Manchester

S. Temple , University of Manchester

pp. 201

Improving Smart Card Security Using Self-Timed Circuits (Abstract)

George Taylor , University of Cambridge

Simon Moore , University of Cambridge

Ross Anderson , University of Cambridge

Robert Mullins , University of Cambridge

Paul Cunningham , University of Cambridge

pp. 211

Keynote Session IV - Chair: Peter Beerel

Taking Asynchronous Design to the Market (PDF)

Uri Cummings , Fulcrum Microsystems Inc.

Andrew Lines , Fulcrum Microsystems Inc.

pp. null

Author Index (PDF)

pp. 219