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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2002)
Manchester, United Kingdom
Apr. 8, 2002 to Apr. 11, 2002
ISSN: 1522-8681
ISBN: 0-7695-1540-1
TABLE OF CONTENTS
Paper Session 1: High-Speed and Energy-Efficient Pipelines - Chair: Jim Garside

Synchronous Interlocked Pipelines (Abstract)

Stanley E. Schuster , IBM T.J. Watson Research Center
Prabhakar N. Kudva , IBM T.J. Watson Research Center
Peter W. Cook , IBM T.J. Watson Research Center
Hans M. Jacobson , IBM T.J. Watson Research Center
Pradip Bose , IBM T.J. Watson Research Center
pp. 3

High-Speed QDI Asynchronous Pipelines (Abstract)

Peter A. Beerel , University of Southern California
Recep O. Ozdag , University of Southern California
pp. 13

Energy-Efficient Pipelines (Abstract)

David Fang , Cornell University
David Biermann , Cornell University
John Teifel , Cornell University
Rajit Manohar , Cornell University
Clint Kelly , Cornell University
pp. 23
Paper Session 2: Novel Self-Timed Circuit Experiments - Chair: Ivan Sutherland

A Negative-Overhead, Self-Timed Pipeline (Abstract)

Mark R. Greenstreet , University of British Columbia
Brian D. Winters , University of British Columbia
pp. 37

An Event Spacing Experiment (Abstract)

Mark Greenstreet , University of British Columbia
Anthony Winstanley , University of British Columbia
Aurelien Garivier , L'Ecole Normale Superieure
pp. 47
Keynote Session I - Chair: Steve Furber
Paper Session 3: Mixed Synchronous/Asynchronous Communication and Design

Clock Synchronization through Handshake Signalling (Abstract)

Joep Kessels , Philips Research
Paul Wielage , Philips Research
Ad Peeters , Philips Research
Suk-Jin Kim , Kwang-Ju Institute of Science and Technology
pp. 59

Point to Point GALS Interconnect (Abstract)

George Taylor , University of Cambridge
Peter Robinson , University of Cambridge
Simon Moore , University of Cambridge
Robert Mullins , University of Cambridge
pp. 69

An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz (Abstract)

Steven M. Nowick , Columbia University
Montek Singh , University of North Carolina at Chapel Hill
Alexander Rylyakov , IBM Thomas J. Watson Research Center
Sergey Rylov , IBM Thomas J. Watson Research Center
Jose A. Tierno , IBM Thomas J. Watson Research Center
pp. 84
Keynote Session II - Chair: Peter Robinson

Nanomagnetic Logic Devices (PDF)

Russell Cowburn , University of Durham
pp. null
Paper Session 4: Timing Analysis and Verification - Chair: Mark Josephs

Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays (Abstract)

Rohan Angrish , Stanford University
Supratik Chakraborty , Indian Institute of Technology, Bombay
pp. 99

Relative Timing Based Verification of Timed Circuits and Systems (Abstract)

Hoshik Kim , University of Southern California
Ken Stevens , Intel Corporation
Peter A. Beerel , University of Southern California
pp. 115
Paper Session 5: High-Level Design and Analysis of Self-Timed Circuits - Luciano Lavagno

Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment (Abstract)

Alex Yakovlev , University of Newcastle upon Tyne
Alexandre Bystrov , University of Newcastle upon Tyne
pp. 127

Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond (Abstract)

Alex Kondratyev , Cadence Berkeley Laboratories
Lawrence Neukom , Verific Design Automation
Alexander Taubin , Boston University
Oriol Roig , Cadence Berkeley Laboratories
Karl Fant , Theseus Research
pp. 149
Keynote Session III

Mobile Applications (PDF)

Nick Foggin , Orange
pp. null
Paper Session 6: Production Testing - Chair: Marly Roncken

Adding Synchronous and LSSD Modes to Asynchronous Circuits (Abstract)

Frank de Beest , University of Twente
Kees van Berkel , Philips Research Laboratories and Eindhoven University of Technology
Ad Peeters , Philips Research Laboratories
pp. 161

Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach (Abstract)

Lief Sorensen , Theseus Logic, Inc.
Amy Streich , Theseus Logic, Inc.
Alex Kondratyev , Cadence Berkeley Laboratory
pp. 171

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems (Abstract)

W. Fichtner , Swiss Federal Institute for Technology
H. Kaeslin , Swiss Federal Institute for Technology
F. Gürkaynak , Swiss Federal Institute for Technology
N. Felber , Swiss Federal Institute for Technology
S. Oetiker , Swiss Federal Institute for Technology
T. Villiger , Swiss Federal Institute for Technology
pp. 181

On-Chip Structures for Timing Measurements and Test (Abstract)

A. V. Yakovlev , Newcastle University
O. V. Maevsky , Newcastle University
G. Russell , Newcastle University
A. Bystrov , Newcastle University
D. J. Kinniment , Newcastle University
pp. 190
Paper Session 7: Security - Chair: Joep Kessels

SPA — A Synthesisable Amulet Core for Smartcard pplications (Abstract)

P. A. Riocreux , University of Manchester
A. Bardsley , University of Manchester
W. J. Bainbridge , University of Manchester
S. Temple , University of Manchester
J. D. Garside , University of Manchester
L. A. Plana , University of Manchester
pp. 201

Improving Smart Card Security Using Self-Timed Circuits (Abstract)

Robert Mullins , University of Cambridge
Paul Cunningham , University of Cambridge
Simon Moore , University of Cambridge
Ross Anderson , University of Cambridge
George Taylor , University of Cambridge
pp. 211
Keynote Session IV - Chair: Peter Beerel

Taking Asynchronous Design to the Market (PDF)

Andrew Lines , Fulcrum Microsystems Inc.
Uri Cummings , Fulcrum Microsystems Inc.
pp. null

Author Index (PDF)

pp. 219
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