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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2001)
Salt Lake City, Utah
Mar. 11, 2001 to Mar. 14, 2001
ISSN: 1522-8681
ISBN: 0-7695-1034-5
TABLE OF CONTENTS
Invited Session 1--Chair: Mark Greenstreet
Paper Session 1: Systems/Arithmetic--Chair: Marc Renaudin

A Low-Power Self-Timed Viterbi Decoder (Abstract)

L.E.M. Brackenbury , University of Manchester
S.B. Furber , University of Manchester
P.A. Riocreux , University of Manchester
M. Cumpstey , University of Manchester
pp. 15

A Multi-Radix Approach to Asynchronous Division (Abstract)

Gianluca Cornetta , Universitat Politecnica de Catalunya
Jordi Cortadella , Universitat Politecnica de Catalunya
pp. 25
Paper Session 2: Experiments--Chair: Ken Stevens

A Practical Comparison of Asynchronous Design Styles (Abstract)

J.D. Garside , The University of Manchester
D.W. Lloyd , STMicroelectronics
pp. 36

GasP: A Minimal FIFO Control (Abstract)

Ivan Sutherland , Sun Microsystems Laboratories
Scott Fairbanks , Sun Microsystems Laboratories
pp. 46

PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI (Abstract)

Kouichi Nagami , NTT Network Innovation Laboratories
Ryusuke Konishi , NTT Network Innovation Laboratories
Minoru Inamori , NTT Network Innovation Laboratories
Norbert Imlig , NTT Network Innovation Laboratories
Hideyuki Ito , NTT Network Innovation Laboratories
Tsunemichi Shiozawa , NTT Network Innovation Laboratories
Kiyoshi Oguri , Nagasaki University
Akira Nagoya , NTT Network Innovation Laboratories
Hiroshi Nakada , NTT Network Innovation Laboratories
pp. 54
Paper Session 3: Synthesis and Verification--Chair: Peter Beerel

Efficient Exact Two-Level Hazard-Free Logic Minimization (Abstract)

Chris Myers , University of Utah
Hans Jacobson , University of Utah
pp. 64
Paper Session 4: Handshaking--Chair: Peter Hofstee

Synchronous Handshake Circuits (Abstract)

Ad Peeters , Philips Research Laboratories
Kees van Berkel , Philips Research Laboratories
pp. 86
Paper Session 5: Communication--Chair: Jo Ebergen

Designing an Asynchronous Bus Interface (Abstract)

Klaus Ully , Philips Semiconductors
Ad Peeters , Philips Research
Markus Feuser , Philips Semiconductors
Joep Kessels , Philips Research
Torsten Kramer , Kramer-Consulting
pp. 108

Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding (Abstract)

W.J. Bainbridge , The University of Manchester
S.B. Furber , The University of Manchester
pp. 118

Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism (Abstract)

D. Shang , University of Newcastle
A. Yakovlev , University of Newcastle
F. Xia , University of Newcastle
pp. 127
Invited Session 2--Chair: Ad Peeters
Paper Session 6: Architecture--Chair: Simon Moore

AMULET3i Cache Architecture (Abstract)

D. Hormdee , University of Manchester
J.D. Garside , University of Manchester
pp. 152

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors (Abstract)

Motokazu Ozawa , The University of Tokyo, Japan
Masashi Imai , The University of Tokyo, Japan
Yoichiro Ueno , Tokyo Denki University, Japan
Takashi Nanya , The University of Tokyo, Japan
Hiroshi Nakamura , The University of Tokyo, Japan
pp. 162

FLEETzero: An Asynchronous Switching Experiment (Abstract)

William S. Coates , Sun Microsystems Laboratories
Jon K. Lexau , Sun Microsystems Laboratories
Ivan E. Sutherland , Sun Microsystems Laboratories
Scott M. Fairbanks , Sun Microsystems Laboratories
Ian W. Jones , Sun Microsystems Laboratories
pp. 173
Paper Session 7: Performance Analysis and Optimization--Chair: Oriol Roig

Designing Fast Asynchronous Circuits (Abstract)

Jon K. Lexau , Sun Microsystems Laboratories
Ivan E. Sutherland , Sun Microsystems Laboratories
pp. 184

Squaring the FIFO in GasP (Abstract)

Jo Ebergen , Sun Microsystems Laboratories
pp. 194

How to Achieve Worst-Case Performance (Abstract)

Brian de Alwis , University of British Columbia
Mark R. Greenstreet , University of British Columbia
pp. 206
Invited Session 3--Chair: Al Davis

Author Index (PDF)

pp. 219
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