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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (2000)
Eilat, Israel
Apr. 2, 2000 to Apr. 6, 2000
ISSN: 1522-8681
ISBN: 0-7695-0586-4
Session I: Theory & Verification Techniques, Chair: Mark Josephs

Formal Verification of Safety Properties in Timed Circuits (Abstract)

Marco A. Pena , Technical University of Catalonia
Alex Kondratyev , Theseus Logic Inc.
Jordi Cortadella , Technical University of Catalonia
Enric Pastor , Technical University of Catalonia
pp. 2

Composing Snippets (Abstract)

Jo Ebergen , Sun Microsystems Laboratories
Igor Benko , University of Waterloo
pp. 23
Session II: Asynchronous Design in Embedded Systems, Chair: Peter Beerel

Applying Asynchronous Circuits in Contactless Smart Cards (Abstract)

Torsten Kramer , MAZ Hamburg
Volker Timm , Philips Semiconductors
Joep Kessels , Philips Research
Gerrit den Besten , Philips Research
Ad Peeters , Philips Research
pp. 36

An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems (Abstract)

Steve Wilcox , University of Cambridge
Peter Robinson , University of Cambridge
Simon Moore , University of Cambridge
George Taylor , University of Cambridge
pp. 45

Practical Design of Globally-Asynchronous Locally-Synchronous Systems (Abstract)

Wolfgang Fichtner , Swiss Federal Institute of Technology
Jens Muttersbach , Swiss Federal Institute of Technology
Thomas Villiger , Swiss Federal Institute of Technology
pp. 52
Session III: Testability, Chair: Jens Sparsø

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder (Abstract)

Marly Roncken , Intel Corporation
Ken Stevens , Intel Corporation
Shai Rotem , Intel Israel
Rajesh Pendurkar , Sun Microsystems
Parimal Pal Chaudhuri , Bengal Engineering College
pp. 62

DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits (Abstract)

Marly Roncken , Intel Corporation
Jo Ebergen , Sun Microsystems Laboratories, Inc.
Philip P. Shirvani , Stanford University
Subhasish Mitra , Stanford University
pp. 73
Session IV: Synthesis, Chair: Ken Stevens

Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL (Abstract)

Luciano Lavagno , Universit? di Udine
Ivan Blunno , Politecnico di Torino
pp. 84

High-Level Asynchronous System Design Using the ACK Framework (Abstract)

Prabhakar Kudva , IBM T.J.Watson Research Center
Hans Jacobson , University of Utah
Ganesh Gopalakrishnan , University of Utah
Erik Brunvand , University of Utah
pp. 93

Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis (Abstract)

Dong-Ik Lee , Kwangju Institute of Science and Technology
Jeong-Gun Lee , Kwangju Institute of Science and Technology
Euiseok Kim , Kwangju Institute of Science and Technology
pp. 104

Asynchronous Design Using Commercial HDL Synthesis Tools (Abstract)

Michiel Ligthart , Theseus Logic
Alex Kondratyev , Theseus Logic
Ross Smith , Theseus Logic
Karl Fant , Theseus Logic
Alexander Taubin , Theseus Logic
pp. 114
Session V: Arbitration & Circuit Techniques, Chair: Tomohiro Yoneda

Priority Arbiters (Abstract)

A. Bystrov , University of Newcastle upon Tyne
A. Yakovlev , University of Newcastle upon Tyne
D.J. Kinniment , University of Newcastle upon Tyne
pp. 128

Asynchronous Communication Mechanisms Using Self-Timed Circuits (Abstract)

D. Shang , University of Newcastle upon Tyne
D.J. Kinniment , University of Newcastle upon Tyne
F. Xia , University of Newcastle upon Tyne
A. Yakovlev , University of Newcastle upon Tyne
A. Bystrov , University of Newcastle upon Tyne
A. Koelmans , University of Newcastle upon Tyne
pp. 150
Session VI: Processor Design, Chair: Doug Edwards

AMULET3i - An Asynchronous System-on-Chip (Abstract)

J.D. Garside , University of Manchester
J. Liu , Cogency Technology Inc.
W.J. Bainbridge , University of Manchester
A. Bardsley , University of Manchester
S. Mohammadi , University of Manchester
S. Temple , University of Manchester
D.W. Lloyd , University of Manchester
J.S. Pepper , University of Manchester
O. Petlin , ASIC Alliance Corporation
D.A. Edwards , University of Manchester
D.M. Clark , University of Manchester
S.B. Furber , University of Manchester
J.V. Woods , University of Manchester
pp. 162

An Instruction Buffer for a Low-Power DSP (Abstract)

M. Lewis , University of Manchester
L. Brackenbury , University of Manchester
pp. 176
Session VII: Pushing the Performance Limit, Chair: Takashi Nanya

VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip (Abstract)

S. A. Huss , Darmstadt University of Technology
O. Hauck , Darmstadt University of Technology
A. Katoch , Darmstadt University of Technology
pp. 188

Low-Latency Asynchronous FIFO's Using Token Rings (Abstract)

Steven M. Nowick , Columbia University
Tiberiu Chelcea , Columbia University
pp. 210

Author Index (PDF)

pp. 221
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