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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (1999)
Barcelona, Spain
Apr. 19, 1999 to Apr. 21, 1999
ISSN: 1522-8681
ISBN: 0-7695-0031-5
TABLE OF CONTENTS
Keynote Session I, Chair: Ganesh Gopalakrishnan
Session I: Verification Techniques, Chair: John Brzozowski
Session II: Low Power/Noise, Chair: Kees van Berkel

Reconfigurable Latch Controllers for Low Power Asynchronous Circuits (Abstract)

J. Garside , University of Manchester
M. Lewis , University of Manchester
L. Brackenbury , University of Manchester
pp. 27

Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications (Abstract)

Alexander Taubin , The University of Aizu
Alex Kondratyev , The University of Aizu
Luciano Lavagno , Politecnico di Torino
Jordi Cortadella , University Polit?cnica de Catalunya
pp. 36
Keynote Session II, Chair: Steve Furber
Session III: Microprocessor Design, Chair: Takashi Nanya

AMULET3 Revealed (Abstract)

S.-H. Chung , University of Manchester
J. D. Garside , University of Manchester,
S. B. Furber , University of Manchester,
pp. 51

RAPPID: An Asynchronous Instruction Length Decoder (Abstract)

Boris Agapiev , Intel Corporation
Marly Roncken , Intel Corporation
Charles Dike , Intel Corporation
Ken Stevens , Intel Corporation
Rakefet Kol , Technion
Peter Beerel , University of Southern California
Chris Myers , University of Utah
Shai Rotem , Intel Corporation
Kenneth Yun , University of California at San Diego
Ran Ginosar , Intel Corporation and Technion
pp. 60

Memory Faults in Asynchronous Microprocessors (Abstract)

D.A. Gilbert , University of Manchester
D.W. Lloyd , University of Manchester
J.D. Garside , University of Manchester
pp. 71
Panel Session
Session IV: Timing Analysis, Chair: Ran Ginosar

Symbolic Time Separation of Events (Abstract)

Tod Amon , Southwest Texas State University
Henrik Hulgaard , Technical University of Denmark
pp. 83

Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice (Abstract)

Sangyun Kim , University of Southern California
Aiguo Xie , University of Southern California
Peter A. Beerel , University of Southern California
pp. 94

Timed Trace Theoretic Verification Using Partial Order Reduction (Abstract)

Tomohiro Yoneda , Tokyo Institute of Technology
Hiroshi Ryu , NEC Corporation
pp. 108
Session V: Synthesis, Chair: Stephen Unger

Projection: A Synthesis Technique for Concurrent Systems (Abstract)

Alain J. Martin , California Institute of Technology
Tak-Kwan Lee , California Institute of Technology
Rajit Manohar , Cornell University
pp. 125
Session VI: Arbitration, Chair: David Kinniment

A Counterflow Pipeline Experiment (Abstract)

Jon Lexau , Sun Microsystems Laboratories
Ian Jones , Sun Microsystems Laboratories
Ivan Sutherland , Sun Microsystems Laboratories
Alex Ridgway , Sun Microsystems Laboratories
Jo Ebergen , Sun Microsystems Laboratories
Bill Coates , Sun Microsystems Laboratories
Scott Fairbanks , Sun Microsystems Laboratories
David Harris , Sun Microsystems Laboratories
pp. 161
Keynote Session III, Chair: Jens Sparsø
Session VII: Pushing the Performance Limit, Chair: Bill Coates

Relative Timing (Abstract)

Ran Ginosar , Intel Corporation and Technion
Shai Rotem , Intel Corporation
Ken Stevens , Intel Corporation
pp. 208

Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT (Abstract)

O. Hauck , Darmstadt University of Technology
S.A. Huss , Darmstadt University of Technology
M. Garg , Darmstadt University of Technology
pp. 219
Session VIII: Theory, Chair: Alex Kondratyev

Analysis and Applications of the XDI model (Abstract)

Willem C. Mallon , University of Groningen
Jan Tijmen Udding , University of Groningen
Tom Verhoeff , Eindhoven University of Technology
pp. 231

A Self-Timed Implementation of Boolean Functions (Abstract)

Tomohiro Yoneda , Tokyo Institute of Technology
Märt Saarepera , Tokyo Institute of Technology
pp. 243
Index

Author Index (PDF)

pp. 251
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