The Community for Technology Leaders
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (1997)
Eindhoven, THE NETHERLANDS
Apr. 7, 1997 to Apr. 10, 1997
ISBN: 0-8186-7922-0
TABLE OF CONTENTS

Welcome Address (PDF)

pp. viii

Reviewers (PDF)

pp. xii
Invited Lectures

Invited Lectures (PDF)

pp. null
Session 1: Pipelines and Meshes

A Result Forwarding Mechanism for Asynchronous Pipelined Systems (Abstract)

D.A. Gilbert , The University of Manchester
J.D. Garside , The University of Manchester
pp. 2

Two-Phase Asynchronous Pipeline Control (Abstract)

S.V. Morton , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
M.J. Liebelt , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
S.S. Appleton , Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
pp. 12

Built-In Self-Testing of Micropipelines (Abstract)

O. A. Petlin , The University of Manchester
S. B. Furber , The University of Manchester
pp. 22

Self-Timed Meshes Are Faster Than Synchronous (Abstract)

M.R. Greenstreet , Dept. of Comput. Sci., British Columbia Univ., Canada
P.B.K. Pang , Dept. of Comput. Sci., British Columbia Univ., Canada
pp. 30
Session 2: Exotic Implementations

Delay Insensitive Logic for RSFQ Superconductor Technology (Abstract)

Stanislav Polonsky , SUNY Stony Brook
Priyadarsan Patra , Intel Corporation
Donald S. Fussell , The University of Texas at Austin
pp. 42

On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic (Abstract)

R. Saletti , University of Pisa
P. Terreni , University of Pisa
R. Mariani , University of Pisa
R. Roncella , University of Pisa
pp. 54
Session 3: Performance Analysis

Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events (Abstract)

Aiguo Xie , University of Southern California
Peter A. Beerel , University of Southern California
pp. 64

Response Time Properties of Some Asynchronous Circuits (Abstract)

Jo Ebergen , University of Waterloo
Robert Berks , University of Waterloo
pp. 76
Session 4: Timing Analysis

Efficient Timing Analysis Algorithms for Timed State Space Exploration (Abstract)

Wendy Belluomini , Computer Science Department, University of Utah, UT
Chris J. Myers , Electrical Engineering Department, University of Utah, UT
pp. 88

Timing Analysis of Extended Burst-Mode Circuits (Abstract)

Supratik Chakraborty , Stanford University
David L. Dill , Stanford University
Kenneth Y. Yun , University of California, San Diego
Kun-Yung Chang , Stanford University
pp. 101

More Accurate Polynomial-Time Min-Max Timing Simulation (Abstract)

David L. Dill , Stanford University
Supratik Chakraborty , Stanford University
pp. 112
Session 5: Design

A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems (Abstract)

Peter Y.K. Cheung , Imperial College of Science, Technology and Medicine
Pedro A. Molina , Imperial College of Science, Technology and Medicine
pp. 126

The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver (Abstract)

Julio Arceo , University of California, San Diego
Peter A. Beerel , University of Southern Calfornia
Kenneth Y. Yun , University of California, San Diego
Ayoob E. Dooply , University of California, San Diego
Vida Vakilotojar , University of Southern Calfornia
pp. 140
Session 6: Formal Methods

Action Systems in Pipelined Processor Design (Abstract)

Juha Plosila , University of Turku, Department of Applied Physics, Finland
Kaisa Sere , Abe Akademi University, Department of Computer Science, Finland
pp. 156

Normal Form in DI-Algebra with Recursion (Abstract)

Paul G. Lucassen , University of Groningen
Indra Polak , University of Groningen
Jan Tijmen Udding , University of Groningen
pp. 167

Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications (Abstract)

Willem C. Mallon , Department of Computing Science, Groningen University, Netherlands
Jan Tijmen Udding , Department of Computing Science, Groningen University, Netherlands
pp. 175
Session 7: Arithmetic

Bundled Data Asynchronous Multipliers with Data Dependent Computation Times (Abstract)

David Kearney , University of South Australia
Neil W. Bergmann , Queensland University of Technology
pp. 186

Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders (Abstract)

Kenneth Y. Yun , University of California, San Diego
Steven M. Nowick , Columbia University
Peter A. Beerel , University of Southern California
Ayoob E. Dooply , University of California, San Diego
pp. 210
Session 9: Synthesis

Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis (Abstract)

Michael Kishinevsky , The University of Aizu, Japan
Luciano Lavagno , Politecnico di Torino, Italy
Alex Kondratyev , The University of Aizu, Japan
Alex Yakovlev , University of Newcastle upon Tyne, United Kingdom
Jordi Cortadella , Universit Politecnica de Catalunya, Spain
pp. 240

Partial order based approach to synthesis of speed-independent circuits. (Abstract)

Enric Pastor , Universitat Politbcnica de Catalunya, Spain
Jordi Cortadella , Universitat Politbcnica de Catalunya, Spain
Marco A. Peña , Universitat Politbcnica de Catalunya, Spain
Alex Yakovlev , University of Newcastle, England
Luciano Lavagno , Politecnico di Torino, Italy
Alex Semenov , University of Newcastle, England
pp. 254
Session 10: Silicon

Designing Asynchronous Standby Circuits for a Low-Power Pager (Abstract)

Paul Marston , Philips Paging
Joep Kessels , Philips Research Laboratories
pp. 268

A FIFO Ring Performance Experiment (Abstract)

Ian W. Jones , Sun Microsyst. Labs., CA, USA
Charles E. Molnar , Sun Microsyst. Labs., CA, USA
William S. Coates , Sun Microsyst. Labs., CA, USA
Jon K. Lexau , Sun Microsyst. Labs., CA, USA
pp. 279

AMULET2e: An Asynchronous Embedded Controller (Abstract)

S. Temple , The University of Manchester
J. Liu , The University of Manchester
P. Day , Cogency Technology Inc.
S. B. Furber , The University of Manchester
J. D. Garside , The University of Manchester
N. C. Paver. , Cogency Technology Inc.
pp. 290
78 ms
(Ver 3.3 (11022016))