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2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (1996)
Aizu-Wakamatsu, Fukushima, JAPAN
Mar. 18, 1996 to Mar. 21, 1996
ISBN: 0-8186-7298-6
TABLE OF CONTENTS

Reviewers (PDF)

pp. x
Session 1: High-Speed Design

A System for Asynchronous High-speed Chip to Chip Communication (Abstract)

Per Torstein Røine , Department of Informatics University of Oslo, N-0316 Oslo, Norway
pp. 2

Dynamic Logic in Four-Phase Micropipelines (Abstract)

J. Liu , The University of Manchester
S. B. Furber , The University of Manchester
pp. 11

High-Performance Asynchronous Pipeline Circuits (Abstract)

K.Y. Yun , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
P.A. Beerel , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
J. Arceo , Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 17
Session 2: Logic Synthesis

An Efficient Algorithm for Deriving Logic Functions of Asynchronous Circuits (Abstract)

Toshiyuki Miyamoto , Kumagai Lab., Department of Electrical Engineering Osaka University
Sadatoshi Kumagai , Kumagai Lab., Department of Electrical Engineering Osaka University
pp. 30

Complete State Encoding Based on the Theory of Regions (Abstract)

Luciano Lavagno , Politecnico di Torino
Michael Kishinevsky , The University of Aizu
Jordi Cortadella , Universitat Politecnica de Catalunya
Alex Kondratyev , The University of Aizu
Alex Yakovlev , University of Newcastle upon Tyne
pp. 36

General Conditions for the Decomposition of State-Holding Elements (Abstract)

Steven M. Burns , Department of Computer Science and Engineering University of Washington
pp. 48
Session 3: Architectural Synthesis

Counterflow Pipeline Based Dynamic Instruction Scheduling (Abstract)

Tony Werner , Asynchronous Systems Research Group Department of Electrical and Computer Engineering University of California - Davis
Venkatesh Akella , Asynchronous Systems Research Group Department of Electrical and Computer Engineering University of California - Davis
pp. 69

Static Scheduling of Instructions on Micronet-based Asynchronous Processors (Abstract)

D. K. Arvind , Department of Computer Science, The University of Edinburgh
V. E. F. Rebello , Department of Computer Science, The University of Edinburgh
pp. 80
Session 4: Formal Methods

Dynamic Hazards and Speed Independent Delay Model (Abstract)

Nozar Tabrizi , University of Adelaide
Michael J. Liebelt , University of Adelaide
Kamran Eshraghian , Faculty of Science and Technology Edith Cowan University
pp. 94

Some Limitations to Speed-Independence in Asynchronous Circuits (Abstract)

Mark B Josephs , School of CISM, South Bank University
Martin E Bush , School of CISM, South Bank University
pp. 104
Session 5: Novel Techniques

Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits (Abstract)

Arjan Bink , Eindhoven University of Technology
Kees van Berkel , Philips Research Laboratories
pp. 122

Pulse-Driven Dual-Rail Logic Gate Family Based on Rapid Single-Flux- Quantum (RSFQ) Devices for Asynchronous Circuits (Abstract)

Yoshio Kameda , Tokyo Institute of Technology,
Itaru Kurosawa , Electrotechnical Laboratory
Masaaki Maezawa , Electrotechnical Laboratory
Takashi Nanya , Tokyo Institute of Technology,
pp. 134

Activity-Monitoring Completion-Detection (AMCD): A New Single Rail Approach to Achieve Self-Timing (Abstract)

E. Grass , School of Electronic and Manufacturing Systems Engineering University of Westminster
I. Kale , School of Electronic and Manufacturing Systems Engineering University of Westminster
R. C. S. Morling , School of Electronic and Manufacturing Systems Engineering University of Westminster
pp. 143
Session 6: Design Automation and Measurements

Using Partial Orders For Trace Theoretic Verification Of Asynchronous Circuits (Abstract)

Takashi Yoshikawa , Department of Computer Science, Tokyo Institute of Technology
Tomohiro Yoneda , Department of Computer Science, Tokyo Institute of Technology
pp. 152

Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems (Abstract)

G. Samuel , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
R. Ginosar , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
R. Kol , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 164
Session 7: Low Power and System Design

The Energy and Entropy of VLSI Computations (Abstract)

Rajit Manohar , California Institute of Technology
Alain J. Martin , California Institute of Technology
Jose A. Tierno , IBM T.J. Watson Research Center Yorktown Heights, NY 10598
pp. 188

A Low-power Asynchronous Data-path for a FIR Filter Bank (Abstract)

Lars S. Nielsen , Technical University of Denmark
Jens Sparsø , University of Utah
pp. 197

The AMULET2e Cache System (Abstract)

S. Temple , The University of Manchester
R. Mehra , The University of Manchester
J.D. Garside , The University of Manchester
pp. 208
Session 8: Logic Optimization

Combining Process Algebras and Petri Nets for the Specification and Synthesis of Asynchronous Circuits (Abstract)

Jordi Cortadella , Department of Computer Architecture Universitat Politecnica de Catalunya
Marco A. Pena , Department of Computer Architecture Universitat Politecnica de Catalunya
pp. 222

Control Resynthesis for Control-Dominated Asynchronous Designs (Abstract)

Bill Lin , IMEC, VSDM division, Kapeldreef 75, B-3001 Leuven, Belgium
Steven Vercauteren , IMEC, VSDM division, Kapeldreef 75, B-3001 Leuven, Belgium
Tilman Kolks , IMEC, VSDM division, Kapeldreef 75, B-3001 Leuven, Belgium
pp. 233

Optimizing average-case delay in technology mapping of burst-mode circuits (Abstract)

K.Y. Yun , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
W.C. Chou , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
P.A. Beerel , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 244
Special Session 3: Emedded Talk

Author Index (PDF)

pp. 265
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