2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (1995)
May 30, 1995 to May 31, 1995
R. van de Wiel , Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands
The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%.
asynchronous circuits; logic testing; VLSI; error detection codes; asynchronous circuits; high-level test evaluation; production fault tests; fault model; high-level circuit description; asynchronous 22 k transistor DCC error corrector IC
R. van de Wiel, "High-level test evaluation of asynchronous circuits", 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, vol. 00, no. , pp. 63, 1995, doi:10.1109/WCADM.1995.514643