The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (2007)
Yokohama
Jan. 23, 2007 to Jan. 26, 2007
ISBN: 1-4244-0629-3
TABLE OF CONTENTS
Papers

Covers (PDF)

pp. C1

Copyright page (PDF)

pp. ii

Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains (Abstract)

Rob A. Rutenbar , Electrical&Computer Engineering, Carnegie Mellon University, United States
pp. vii

Meeting with the Forthcoming IC Design ? The Era of Power, Variability and NRE Explosion and a Bit of the Future ? (Abstract)

Takayasu Sakurai , Center for Collaborative Research, and Institute of Industrial Science, University of Tokyo, Japan
pp. viii

How Foundry can Help Improve your Bottom-Line? Accuracy Matters! (Abstract)

Fu-Chieh Hsu , Vice President, Design and Technology Platform, Taiwan Semiconductor Manufacturing Company, Taiwan
pp. ix

Industry Liaison (PDF)

pp. xxiv

List of Reviewers (PDF)

pp. xxv-xxvi

Contents (PDF)

pp. xxvii-xliv

Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process (Abstract)

Charles Chiang , Synopsys Inc., Mountain View, CA, USA. Email: clc@synopsys.com
Jianfeng Luo , Synopsys Inc., Mountain View, CA, USA. Email: jianfeng@synopsys.com
Subarna Sinha , Synopsys Inc., Mountain View, CA, USA. Email: subarna@synopsys.com
pp. 1-6

Fast and Accurate OPC for Standard-Cell Layouts (Abstract)

Liang Deng , Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign. ldeng@u
Martin D. F. Wong , Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign. mdfwong
David M. Pawlowski , Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign. dmpawlo
pp. 7-12

Coupling-aware Dummy Metal Insertion for Lithography (Abstract)

null Liang Deng , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana-Champaign, IL
M.D.F. Wong , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana-Champaign, IL
pp. 13-18

Fast Buffer Insertion for Yield Optimization Under Process Variations (Abstract)

Ruiming Chen , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208
Hai Zhou , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208
pp. 19-24

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield (Abstract)

Xu Xu , CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:
Andrew B. Kahng , CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:
Ganesh Venkataraman , ECE Department, Texas A&M University, College Station, TX 77843-3182. Tel: 979-847-8768, Fax: 979-84
Bao Liu , CSE Department, UC San Diego, La Jolla, CA 92093-0114. Tel: 858-534-7890, Fax: 858-534-7029, e-mail:
Jiang Hu , ECE Department, Texas A&M University, College Station, TX 77843-3182. Tel: 979-847-8768, Fax: 979-84
pp. 24-31

Control-Flow Aware Communication and Conflict Analysis of Parallel Processes (Abstract)

Oliver Bringmann , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. bringman@fzi.de
Alexander Viehl , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. viehl@fzi.de
Axel Siebenborn , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany. siebenbo@fzi.de
Wolfgang Rosenstiel , FZI Forschungszentrum Informatik, Haid-und-Neu-Str. 10-14, 76131 Karlsruhe, Germany; Universit?t T?
pp. 32-37

Software Performance Estimation in MPSoC Design (Abstract)

F.R. Wagner , UFRGS, Inst. de Informatica, Porto Alegre
M. Oyamada , UFRGS, Inst. de Informatica, Porto Alegre
pp. 38-43

Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS (Abstract)

null Soonhoi Ha , Dept. of Electr. Eng.&Comput. Sci., Seoul Nat. Univ.
null Woo-Chul Jeun , Dept. of Electr. Eng.&Comput. Sci., Seoul Nat. Univ.
pp. 44-49

Creating Explicit Communication in SoC Models Using Interactive Re-Coding (Abstract)

Rainer Domer , Center for Embedded Computer Systems, University of California, Irvine, California, USA. doemer@cecs
Pramod Chandraiah , Center for Embedded Computer Systems, University of California, Irvine, California, USA. pramodc@cec
Junyu Peng , Center for Embedded Computer Systems, University of California, Irvine, California, USA. pengj@cecs.
pp. 50-55

System Architecture for Software Peripherals (Abstract)

S. Choudhuri , Center for Embedded Comput. Syst., California Univ., Irvine, CA
T. Givargis , Center for Embedded Comput. Syst., California Univ., Irvine, CA
pp. 56-61

A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates (Abstract)

Zeyi Wang , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
Wenjian Yu , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China. Tel: 86-1
Xiren Wang , Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
pp. 62-67

Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers (Abstract)

T. Ragheb , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
A. Nieuwoudt , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
Y. Massoud , Dept. of Electr.&Comput. Eng., Rice Univ., Houston, TX
pp. 68-73

PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool (Abstract)

Michael Chan , School of ITEE, University of Queensland, Brisbane, 4067. e-mail: mchan@itee.uq.edu.au
Yong Ding , Nanosilicon Pty Ltd, Brisbane, 4113
Adam Postula , School of ITEE, University of Queensland, Brisbane, 4067
pp. 74-79

A Programmable Fully-Integrated GPS receiver in 0.18?m CMOS with Test Circuits (Abstract)

Ali Fotowat-Ahmady , RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:
Mahta Jenabi , RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:
Noushin Riahi , RF IC designer, Unistar Micro Technology Inc, Richmond Hill, ON L4C 0K1. Tel: +1-905-780-1347, Fax:
pp. 80-85

Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches (Abstract)

S. Bhunia , Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH
D. Saab , Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH
M. Tabib-Azar , Dept. of Electr. Eng.&Comput. Sci., Case Western Reserve Univ., Cleveland, OH
pp. 86-91

A 1Tb/s 3W Inductive-Coupling Transceiver Chip (Abstract)

T. Kuroda , Keio Univ., Tokyo
N. Miura , Keio Univ., Tokyo
pp. 92-93

22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar Sensors (Abstract)

Ahmet Oncu , School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan
Minoru Fujishima , School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan. fujishima@axcel.k.u-tokyo.ac.j
B.B.M. Wasanthamala Badalawa , School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan
Tong Wang , School of Frontier Sciences, The University of Tokyo, Kashiwa, Japan
pp. 94-95

A 2.8-V Multibit Complex Bandpass ??AD Modulator in 0.18?m CMOS (Abstract)

H. Hagiwara , Dept. of Electron. Eng., Gunma Univ.
H. Kobayashi , Dept. of Electron. Eng., Gunma Univ.
A. Hayakawa , Dept. of Electron. Eng., Gunma Univ.
H. Wada , Dept. of Electron. Eng., Gunma Univ.
H. San , Dept. of Electron. Eng., Gunma Univ.
Y. Jingu , Dept. of Electron. Eng., Gunma Univ.
pp. 96-97

A Wideband CMOS LC-VCO Using Variable Inductor (Abstract)

K. Masu , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
K. Ohashi , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
K. Okada , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
Y. Ito , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
Y. Yoshihara , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
pp. 98-99

Design of Active Substrate Noise Canceller using Power Supply di/dt Detector (Abstract)

Toru Nakura , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J
Makoto Ikeda , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J
Kunihiro Asada , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J
Taisuke Kazama , Department of Electronic Engineering, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, J
pp. 100-101

Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation (Abstract)

S. Fukuda , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
K. Masu , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
D. Kawazoe , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
K. Okada , Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama
pp. 104-105

Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems (Abstract)

M. Fujishima , Sch. of Frontier Sci., Tokyo Univ., Kashiwa
Ivan C.H. Ivan Chee Hong Lai , Sch. of Frontier Sci., Tokyo Univ., Kashiwa
pp. 106-107

Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique (Abstract)

Koji Kotani , Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85
Shigetoshi Sugawa , Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85
Md. Ashfaquzzaman Khan , Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85
Tadahiro Ohmi , New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,
Roel Pantonial , Graduate School of Engineering, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai, 980-85
Naoto Miyamoto , New Industry Creation Hatchery Center, Tohoku University, Aza Aoba 6-6-10, Aramaki, Aoba-ku, Sendai,
pp. 108-109

Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes (Abstract)

Chih-Wei Liu , Department of Electronics Engineering, National Chiao Tung University, Taiwan
Li-Chun Lin , Department of Electronics Engineering, National Chiao Tung University, Taiwan
Shih-Hao Ou , Department of Electronics Engineering, National Chiao Tung University, Taiwan
Siang-Den Deng , Department of Electronics Engineering, National Chiao Tung University, Taiwan
Tay-Jyi Lin , Department of Electronics Engineering, National Chiao Tung University, Taiwan
pp. 110-111

A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform (Abstract)

Sheng-Tsung Hsu , Department of Computer Science, National Tsing Hua University, Taiwan
Tzu-Jen Lo , Department of Computer Science, National Tsing Hua University, Taiwan
Chun-Hsin Lee , Department of Computer Science, National Tsing Hua University, Taiwan
Yuan-Chun Lin , Department of Computer Science, National Tsing Hua University, Taiwan
Kai-Yuan Jan , Department of Computer Science, National Tsing Hua University, Taiwan
Yung-Hung Chang , Department of Computer Science, National Tsing Hua University, Taiwan
Ping Chao , Department of Computer Science, National Tsing Hua University, Taiwan
Wei-Cheng Hung , Department of Computer Science, National Tsing Hua University, Taiwan
Huan-Kai Peng , Department of Computer Science, National Tsing Hua University, Taiwan
Jian-Wen Chen , Department of Computer Science, National Tsing Hua University, Taiwan
pp. 112-113

Configurable AMBA On-Chip Real-Time Signal Tracer (Abstract)

Chung-Fu Kao , Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.
Chi-Hung Lin , Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.
Ing-Jer Huang , Dept. of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan.
pp. 114-115

Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic (Abstract)

S. Matsunaga , Res. Inst. of Electr. Commun., Tohoku Univ., Sendai
T. Hanyu , Res. Inst. of Electr. Commun., Tohoku Univ., Sendai
pp. 116-117

A Multi-Drop Transmission-Line Interconnect in Si LSI (Abstract)

Kazuya Masu , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh
Kenichi Okada , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh
Hiroyuki Ito , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh
Takashi Sato , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh
Junki Seita , Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokoh
pp. 118-119

A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology (Abstract)

H. Onodera , Dept. of Commun.&Comput. Eng., Kyoto Univ.
A. Tsuchiya , Dept. of Commun.&Comput. Eng., Kyoto Univ.
T. Kuboki , Dept. of Commun.&Comput. Eng., Kyoto Univ.
pp. 120-121

A 90nm 8?16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations (Abstract)

K. Katsuki , Dept. of Commun.&Comput. Engeineering, Kyoto Univ.
M. Kotani , Dept. of Commun.&Comput. Engeineering, Kyoto Univ.
H. Onodera , Dept. of Commun.&Comput. Engeineering, Kyoto Univ.
Y. Sugihara , Dept. of Commun.&Comput. Engeineering, Kyoto Univ.
K. Kobayashi , Dept. of Commun.&Comput. Engeineering, Kyoto Univ.
pp. 122-123

A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (Abstract)

F. Kobayashi , Dept. of Syst. Innovation&Informatics, Kyushu Inst. of Technol., Fukuoka
M. Watanabe , Dept. of Syst. Innovation&Informatics, Kyushu Inst. of Technol., Fukuoka
pp. 124-125

Low-Power High-Speed 180-nm CMOS Clock Drivers (Abstract)

T. Enomoto , Chuo Univ., Tokyo
N. Kobayashi , Chuo Univ., Tokyo
S. Nagayama , Chuo Univ., Tokyo
pp. 126-127

Fast Analytic Placement using Minimum Cost Flow (Abstract)

Ameya R. Agnihotri , SUNY Binghamton Computer Science Department, Box 6000, Binghamton NY 13902. email: ameya@acm.org
Patrick H. Madden , SUNY Binghamton Computer Science Department, Box 6000, Binghamton NY 13902. email: pmadden@acm.org
pp. 128-134

FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control (Abstract)

null Min Pan , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
C. Chu , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
N. Viswanathan , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
pp. 135-140

ECO-system: Embracing the Change in Placement (Abstract)

Jarrod A. Roy , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, MI 48109-2121. royj@um
Igor L. Markov , The University of Michigan, Department of EECS, 2260 Hayward Ave., Ann Arbor, MI 48109-2121. imarkov
pp. 147-152

Bisection Based Placement for the X Architecture (Abstract)

Satoshi Ono , Computer Science Department, SUNY Binghamton, Box 6000, Binghamton NY 13902. satoshi@binghamton.edu
Patrick H. Madden , Computer Science Department, SUNY Binghamton, Box 6000, Binghamton NY 13902. pmadden@acm.org
Sameer Tilak , San Diego Supercomputer Center. sameer@sdsc.edu
pp. 153-158

Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems (Abstract)

Eui-Young Chung , School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. eychung@yonse
Minje Jun , School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. jjuninho@yons
Kwanhu Bang , School of Electrical and Electronic Engineering, Yonsei University, Republic of Korea. lamar49@yonse
Naehyuck Chang , School of Computer Science&Engineering, Seoul National University, Republic of Korea. naehyuck@snu.a
Hyuk-Jun Lee , Cisco Systems Incorporation, U.S.A. hyukjunl@yahoo.com
pp. 159-164

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses (Abstract)

Bu-Ching Lin , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.
Jing-Yang Jou , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.
Juinn-Dar Huang , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.
Geeng-Wei Lee , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. kurt@eda.ee.
pp. 165-170

Topology exploration for energy efficient intra-tile communication (Abstract)

Antonis Papanikolaou , IMEC v.z.w., Kapeldreef 75, 3001 Leuven, Belgium
Jin Guo , IMEC v.z.w., Kapeldreef 75, 3001 Leuven, Belgium; Katholieke Universiteit Leuven, Kasteelpark Arenbe
Francky Catthoor , IMEC v.z.w., Kapeldreef 75, 3001 Leuven, Belgium; Katholieke Universiteit Leuven, Kasteelpark Arenbe
pp. 178-183

Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms (Abstract)

Goran Konjevod , Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: goran@asu.e
Karam S. Chatha , Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: kchatha@asu
Krishnan Srinivasan , Department of CSE, PO BOX 875406, Arizona State University, Tempe, AZ 85287-5406. Email: ksrinivasan
pp. 184-190

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation (Abstract)

null Di Long , DCST, Tsinghua Univ., Beijing
null Sheqin Dong , DCST, Tsinghua Univ., Beijing
null Jiayi Liu , DCST, Tsinghua Univ., Beijing
null Xianlong Hong , DCST, Tsinghua Univ., Beijing
null Yuchun Ma , DCST, Tsinghua Univ., Beijing
pp. 191-196

A Graph Reduction Approach to Symbolic Circuit Analysis (Abstract)

null Guoyong Shi , Sch. of Microelectron., Shanghai Jiao Tong Univ.
null Weiwei Chen , Sch. of Microelectron., Shanghai Jiao Tong Univ.
pp. 197-202

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic (Abstract)

Yu Song , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China
Xuan Zeng , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China
Wai-Shing Luk , luk@fudan.edu.cn
Pushan Tang , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China
Xuexin Liu , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R.China
pp. 203-208

Structured Placement with Topological Regularity Evaluation (Abstract)

Shigetoshi Nakatake , Department of Information and Media Sciences, University of Kitakyushu, 1-1 Hibikino, Wakamatsu, Kit
pp. 215-220

Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM (Abstract)

Keh-Jeng Chang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Jun-Fu Huang , Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.
Victor C.Y. Chang , Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.
Sally Liu , Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.
Kelvin Y.Y. Doong , Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu Science-Based Industrial Park, Taiwan, R.
pp. 221-225

DFM/DFY practices during physical designs for timing, signal integrity, and power (Abstract)

null Ke-Cheng Chu , Global UniChip Corp., Hsinchu
null Cheng-Hong Tsai , Global UniChip Corp., Hsinchu
null Shi-Hao Chen , Global UniChip Corp., Hsinchu
null Jiing-Yuan Lin , Global UniChip Corp., Hsinchu
pp. 232-237

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability (Abstract)

Ting-Chi Wang , Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu
Ming-Chao Tsai , Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu
Chung-Wei Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. enorm
Tai-Chen Chen , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan. tcche
Yao-Wen Chang , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan; Depar
Kuang-Yao Lee , Department of Computer Science, National Tsing Hua University, Hsinchu 300, Taiwan. enorm@eda.ee.ntu
pp. 238-243

A Novel Performance-Driven Topology Design Algorithm (Abstract)

Priyadarshan Patra , Intel Corporation, Hillsboro, OR 97124. priyadarshan.patra@intel.com
Chris Chu , Electrical and Computer Engineering Dept., Iowa State University, Ames, IA 50011. Email: cnchu@iasta
Min Pan , Electrical and Computer Engineering Dept., Iowa State University, Ames, IA 50011. Email: panmin@iast
pp. 244-249

FastRoute 2.0: A High-quality and Efficient Global Router (Abstract)

C. Chu , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
null Min Pan , Dept. of Electr.&Comput. Eng., Iowa State Univ., Ames, IA
pp. 250-255

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm (Abstract)

Zhen Cao , Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62
Lei He , Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407, e-mail:
Yu Hu , Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407, e-mail:
Jinjun Xiong , Electrical Engineering Department, UCLA, Los Angeles, CA, 90095, USA. Phone: (310) 267-5407; IBM Res
Xianlong Hong , Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62
Tong Jing , Computer Science&Technology Department, Tsinghua University, Beijing 100084, China. Phone: +86-10-62
pp. 256-261

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction (Abstract)

Pei-Ci Wu , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.
Jhih-Rong Gao , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.
Ting-Chi Wang , Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan. g944310@oz.nthu.edu.
pp. 262-267

A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks (Abstract)

H. Murata , Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka
null Shuting Li , Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka
Y. Takashima , Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka
null Tan Yan , Graduate Sch. of Environ. Eng., Kitakyushu Univ., Fukuoka
pp. 268-273

LEAF: A System Level Leakage-Aware Floorplanner for SoCs (Abstract)

N.D. Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA
A. Gupta , Center for Embedded Comput. Syst., California Univ., Irvine, CA
F.J. Kurdahi , Center for Embedded Comput. Syst., California Univ., Irvine, CA
pp. 274-279
Papers

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units (Abstract)

Masaaki Abe , Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa
Yoshinori Takeuchi , Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa
Masaharu Imai , Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa
Takeshi Shiro , Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa
Keishi Sakanushi , Graduate School of Information Science and Technology, Osaka University, 1-5, Yamada-oka, Suita, Osa
pp. 286-291

Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture (Abstract)

Masahiko Yoshimoto , Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8
Hiroshi Kawaguchi , Department of Computer and Systems Engineering, Kobe University, Kobe, Hyogo 657-8501. Tel: +81-78-8
Kentaro Kawakami , Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit
Mitsuhiko Kuroda , Department of Informatics and Electronics, Graduate School of Science and Technology, Kobe Universit
pp. 292-297

Architectural Optimizations for Text to Speech Synthesis in Embedded Systems (Abstract)

A. Basu , Dept. of Comput. Sci.&Eng., Indian Inst. of Technol., Kharagpur
S. Dey , Dept. of Comput. Sci.&Eng., Indian Inst. of Technol., Kharagpur
M. Kedia , Dept. of Comput. Sci.&Eng., Indian Inst. of Technol., Kharagpur
pp. 298-303

Deeper Bound in BMC by Combining Constant Propagation and Abstraction (Abstract)

Yakir Vizel , Logic and Validation Technology, Intel Corporation, Haifa, Israel
Limor Fix , Logic and Validation Technology, Intel Corporation, Haifa, Israel
Yael Zbar , Logic and Validation Technology, Intel Corporation, Haifa, Israel
Moshe Vardi , Rich University, Houston, Tx
Tamir Heyman , Logic and Validation Technology, Intel Corporation, Haifa, Israel; Carnegie Mellon University, Pitts
Ranan Fraer , Logic and Validation Technology, Intel Corporation, Haifa, Israel
pp. 304-309

Efficient BMC for Multi-Clock Systems with Clocked Specifications (Abstract)

M.K. Ganai , NEC Labs. America, Princeton, NJ
A. Gupta , NEC Labs. America, Princeton, NJ
pp. 310-315

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation (Abstract)

Marc Boule , McGill University, Montr?al, Qu?bec, Canada. marc.boule@elf.mcgill.ca
Zeljko Zilic , McGill University, Montr?al, Qu?bec, Canada. zeljko.zilic@mcgill.ca
pp. 324-329

Model-based Programming Environment of Embedded Software for MPSoC (Abstract)

Soonhoi Ha , School of Computer Science and Engineering, Seoul National University, Seoul, 151-742, KOREA. Tel: 8
pp. 330-335

RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip (Abstract)

S. Honda , Graduate Sch. of Inf. Sci., Nagoya Univ.
pp. 336-341

Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems (Abstract)

Jian-Jia Chen , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw
Chuan-Yue Yang , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw
Chi-Sheng Shih , Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiw
pp. 342-349

Towards scalable and secure execution platform for embedded systems (Abstract)

Masato Edahiro , System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1
Inoue Hiroaki , System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1
Junji Sakai , System Devices Research Laboratories, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1
pp. 350-354

Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation (Abstract)

Mehboob Alam , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Yehia Massoud , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Arthur Nieuwoudt , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
pp. 373-378

Frequency Selective Model Order Reduction via Spectral Zero Projection (Abstract)

Arthur Nieuwoudt , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Yehia Massoud , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Mehboob Alam , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
pp. 379-383

Abstract, Multifaceted Modeling of Embedded Processors for System Level Design (Abstract)

Gunar Schirner , Center for Embedded Computer Systems, University of California, Irvine, USA. hschirne@cecs.uci.edu
Andreas Gerstlauer , Center for Embedded Computer Systems, University of California, Irvine, USA. gerstl@cecs.uci.edu
Rainer Domer , Center for Embedded Computer Systems, University of California, Irvine, USA. doemer@cecs.uci.edu
pp. 384-389

Automating Logic Rectification by Approximate SPFDs (Abstract)

null Yu-Shen Yang , Dept. of Electr.&Comput. Eng., Toronto Univ., Ont.
pp. 402-407

BddCut: Towards Scalable Symbolic Cut Enumeration (Abstract)

Jianwen Zhu , Department Electrical and Computer Engineering, University of Toronto, Toronto, Canada. e-mail: jzhu
Andrew C. Ling , Department Electrical and Computer Engineering, University of Toronto, Toronto, Canada. e-mail: alin
Stephen D. Brown , Altera Corporation, Toronto Technology Centre, Toronto, Canada. e-mail: sbrown@altera.com
pp. 408-413

Node Mergers in the Presence of Don't Cares (Abstract)

Igor L. Markov , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. imarkov@umich.edu
Stephen M. Plaza , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. splaza@umich.edu
Kai-hui Chang , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. changkh@umich.edu
Valeria Bertacco , EECS Department, University of Michigan, Ann Arbor, MI 48109-2121. valeria@umich.edu
pp. 414-419

Synthesis of Reversible Sequential Elements (Abstract)

Chun-Yao Wang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan R.O.C. mr934327@cs.nt
Min-Lun Chuang , Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan R.O.C. mr934327@cs.nt
pp. 420-425

Recognition of Fanout-free Functions (Abstract)

null Tsung-Lin Lee , Dept. of Comput. Sci., National Tsing Hua Univ., HsinChu
null Chun-Yao Wang , Dept. of Comput. Sci., National Tsing Hua Univ., HsinChu
pp. 426-431

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies (Abstract)

Georges G.E. Gielen , ESAT-MICAS, Department of Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium. g
pp. 432-437

Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits (Abstract)

S. Yoshitomi , Microelectron. Centre, Toshiba Corp. Semicond. Co., Kawasaki
pp. 438-441

Advanced tools for simulation and design of oscillators/PLLs (Abstract)

J. Roychowdhury , Dept. of Electr.&Comput. Eng., Minnesota Univ., Minneapolis, MN
null Xiaolue Lai , Dept. of Electr.&Comput. Eng., Minnesota Univ., Minneapolis, MN
pp. 442-449

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects (Abstract)

Ying Zhou , Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843
Yuxin Tian , Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843
Frank Liu , IBM Austin Research Laboratory, 11501 Burnet Rd., Austin, Texas 78758
Weiping Shi , Department of Electrical Engineering, Texas A&M University, College Station, Texas 77843
Zhuo Li , Pextra Corporation, 2900B Longmire Drive, College Station, Texas 77845
pp. 450-455

Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion (Abstract)

null Youngmin Kima , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
D. Petranovic , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
D. Sylvestera , Dept. of Electr. Eng.&Comput. Sci., Michigan Univ., Ann Arbor, MI
pp. 456-461

New Block-Based Statistical Timing Analysis Approaches Without Moment Matching (Abstract)

Hai Zhou , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208
Ruiming Chen , Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208
pp. 462-467

Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method (Abstract)

Michael Marefat , Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax
Janet Wang , Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax
Alexander Mitev , Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax
Dongsheng Ma , Electrical Engineering Department, University of Arizona, Tucson, AZ - 85716. Tel: 520-621-2434, Fax
pp. 468-473

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations (Abstract)

Xuan Zeng , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China. x
Charles Chiang , Advanced Technology Group, Synopsys Inc., Mountain View, CA 94043, USA
Dian Zhou , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China; E
Jun Tao , ASIC&System State Key Lab., Microelectronics Dept., Fudan University, Shanghai 200433, P.R. China
Wei Cai , Department of Mathematics, University of North Carolina, Charlotte, Charlotte, NC 28233, USA
Yangfeng Su , Mathematics Dept., Fudan University, Shanghai 200433, P.R. China
pp. 474-479

Retiming for Synchronous Data Flow Graphs (Abstract)

C. Lin , Northwestern Univ., Evanston, IL
J. Wang , Northwestern Univ., Evanston, IL
H. Zhou , Northwestern Univ., Evanston, IL
P. Banerjee , Northwestern Univ., Evanston, IL
N. Liveris , Northwestern Univ., Evanston, IL
pp. 480-485

Signal-to-Memory Mapping Analysis for Multimedia Signal Processing (Abstract)

Florin Balasa , Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.
Hongwei Zhu , Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.
Ilie I. Luican , Dept. of Computer Science, University of Illinois, Chicago, Chicago, IL 60607, U.S.A.
pp. 486-491

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip (Abstract)

R. Govindarajan , Supercomputer Education&Research Centre, Indian Institute of Science, Bangalore, 560 012, India. gov
C.P. Ravikumar , Texas Instruments India Ltd., C.V. Raman Nagar, Bangalore, 560 091, India. ravikumar@ti.com
T.S. Rajesh Kumar , Texas Instruments India Ltd., C.V. Raman Nagar, Bangalore, 560 091, India. srk@ti.com
pp. 492-497

A Run-Time Memory Protection Methodology (Abstract)

Bart Vermeulen , NXP Semiconductors, Research, High Tech Campus 5, 5656 AE Eindhoven, The Netherlands. bart.vermeulen
Nagaraju Bussa , Philips Research, Philips Innovation Campus, # 1, Murphy Road, Ulsoor 560008, Bangalore, India. naga
Udaya Seshua , NXP Semiconductors, BL Personal, Millenia `D' Block, # 1, Murphy Road, Ulsoor 560008, Bangalore, Ind
pp. 498-503

Short-Circuit Compiler Transformation: Optimizing Conditional Blocks (Abstract)

Alex Nicolau , Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv
Mohammad Ali Ghodrat , Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv
Tony Givargis , Department of Computer Sciences, Center for Embedded Computer Systems, University of California, Irv
pp. 504-510

Optimization of Arithmetic Datapaths with Finite Word-Length Operands (Abstract)

P. Kalla , Electr.&Comput. Eng., Utah Univ., Salt Lake, UT
S. Gopalakrishnan , Electr.&Comput. Eng., Utah Univ., Salt Lake, UT
pp. 511-516

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection (Abstract)

B. M. Al-Hashimi , ESD, School of ECS, University of Southampton, Southampton, UK. bmah@ecs.soton.ac.uk
M. A. Ochoa-Montiel , ESD, School of ECS, University of Southampton, Southampton, UK. mao02r@ecs.soton.ac.uk
P. Kollig , Home Innovation Centre Southampton, NXP Semiconductors, Southampton, UK
pp. 517-522

A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications (Abstract)

Yazhuo Dong , Department of Computer Science, National University of Defence Technology, Changsha, P.R. China, 410
Yong Dou , Department of Computer Science, National University of Defence Technology, Changsha, P.R. China, 410
pp. 523-528

High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs (Abstract)

Jason Cong , Computer Science Department, University of California, Los Angeles. cong@cs.ucla.edu
Zhiru Zhang , Computer Science Department, University of California, Los Angeles. zhiruz@cs.ucla.edu
Yiping Fan , Computer Science Department, University of California, Los Angeles. fanyp@cs.ucla.edu
Deming Chen , Department of ECE, University of Illinois, Urbana-Champaign. dchen@uiuc.edu
pp. 529-534

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams (Abstract)

S. Nagayama , Dept. of Comput. Eng., Hiroshima City Univ.
pp. 535-540

An Efficient Computation of Statistically Critical Sequential Paths Under Retiming (Abstract)

Sung Kyu Lim , Georgia Institute of Technology, Atlanta, Georgia, USA. limsk@ece.gatech.edu
Mongkol Ekpanyapong , Intel Corporation, Folsom, California, USA. mongkol.ekpanyapong@intel.com
Xin Zhao , Georgia Institute of Technology, Atlanta, Georgia, USA. xzhao@ece.gatech.edu
pp. 547-552

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design (Abstract)

Sanghamitra Roy , ECE Department, University of Wisconsin-Madison. roy1.wisc.edu
Charlie Chung-Ping Chen , EE Department, National Taiwan University. cchen@cc.ee.ntu.edu.tw
pp. 559-564

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies (Abstract)

Zhangcai Huang , Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
Hong Yu , Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
Atsushi Kurokawa , Sanyo Semiconductor Co., Ltd, Gunma, 370-0596 Japan
Yasuaki Inoue , Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa
pp. 565-570

Flow-Through-Queue based Power Management for Gigabit Ethernet Controller (Abstract)

Hwisung Jung , Dept. of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. e-mail: h
Massoud Pedram , Dept. of Electrical Engineering, University of Southern California, Los Angeles, CA 90089. e-mail: p
Andy Hwang , Enterprise Networking Group, Broadcom Corporation, Irvine, CA 92618. e-mail: ahwang@broadcom.com
pp. 571-576

Approximation Algorithm for Process Mapping on Network Processor Architectures (Abstract)

C. Ostler , Dept. of Comput. Sci.&Eng., Arizona State Univ., Tempe, AZ
pp. 577-582

Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture (Abstract)

Zahid Khan , System Level Integration Group, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, Scot
Tughrul Arslan , System Level Integration Group, The University of Edinburgh, Mayfield Road, Edinburgh, EH9 3JL, Scot
pp. 583-588

VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond (Abstract)

Tughrul Arslan , School of Electronics and Engineering. University of Edinburgh, King's Buildings Mayfield Rd, Edinbu
Imran Ahmed , School of Electronics and Engineering. University of Edinburgh, King's Buildings Mayfield Rd, Edinbu
pp. 589-594

A High-Throughput Low-Power AES Cipher for Network Applications (Abstract)

null Shin-Yi Lin , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
pp. 595-600

Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands (Abstract)

A.K. Verma , Sch. of Comput.&Commun. Sci., Ecole Polytechnique Federale de Lausanne
pp. 601-608

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation (Abstract)

Cheoljoo Jeong , Department of Computer Science, Columbia University, New York, NY, 10027, USA. Email: cjeong@cs.colu
Steven M. Nowick , Department of Computer Science, Columbia University, New York, NY, 10027, USA. Email: nowick@cs.colu
pp. 622-627

Safe Delay Optimization for Physical Synthesis (Abstract)

null Kai-hui Chang , Dept. of EECS, Michigan Univ., Ann Arbor, MI
pp. 628-633

Overview on Low Power SoC Design Technology (Abstract)

Kimiyoshi Usami , Dept. of Information Science and Engineering, Shibaura Institute of Technology, Tokyo 135-8548, Japa
pp. 634-636

Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware (Abstract)

M. Hase , Dept. of Syst. Design 3, Renesas Technol. Corp., Tokyo
pp. 637-643

Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G) (Abstract)

S. Matsuo , Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan
K. Mori , Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan
M. Suzuki , Toshiba Corporation Digital Media Network Company, 2-9 Suehiro-Cho, Ome, Tokyo 198-8710, Japan
A. Asano , Toshiba Corporation Digital Media Network Company, 2-9 Suehiro-Cho, Ome, Tokyo 198-8710, Japan
Y. Ohara , Toshiba Corporation Semiconductor Company, 580-1 Horikawa-Cho, Saiwai-ku, Kawasaki 212-8520, Japan
pp. 644-648

Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier" (Abstract)

Masaya Sumita , 1 Kotari-Yakemachi Nagaokakyo, Kyoto, 617-8520 Japan
Masaitsu Nakajima , Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na
Tetsu Hosoki , Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na
Takao Yamamoto , Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na
Masayuki Yamasaki , Strategic Semiconductor Development Center, Matsushita Electric Industrial Co., Ltd, 3-1-1 Yagumo-Na
pp. 649-653

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits (Abstract)

null Hyung-Ock Kim , Dept. of Electr. Eng., KAIST, Daejeon
null Sewan Heo , Dept. of Electr. Eng., KAIST, Daejeon
null Youngsoo Shin , Dept. of Electr. Eng., KAIST, Daejeon
pp. 654-659

Runtime leakage power estimation technique for combinational circuits (Abstract)

null Yu-Shiang Lin , Electron. Eng.&Comput. Sci., Michigan Univ.
D. Sylvester , Electron. Eng.&Comput. Sci., Michigan Univ.
pp. 660-665

Logic and Layout Aware Voltage Island Generation for Low Power Design (Abstract)

Liangpeng Guo , EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Yici Cai , EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Xianlong Hong , EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Qiang Zhou , EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China
pp. 666-671

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost (Abstract)

null Jr-Luen Tzeng , Dept. of Electron. Eng., National Changhua Univ. of Educ.
null Kuang-Yao Chen , Dept. of Electron. Eng., National Changhua Univ. of Educ.
null Tsung-Yi Wu , Dept. of Electron. Eng., National Changhua Univ. of Educ.
pp. 672-677

A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs (Abstract)

M. Elmasry , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
H. Hassan , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
M. Anis , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
pp. 678-683

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect (Abstract)

null Rui Shi , Dept. of Comput.&Sci. Eng., California Univ., La Jolla, CA
null Chung-Kuan Cheng , Dept. of Comput.&Sci. Eng., California Univ., La Jolla, CA
null Haikun Zhu , Dept. of Comput.&Sci. Eng., California Univ., La Jolla, CA
pp. 684-689

Delay Uncertainty Reduction by Interconnect and Gate Splitting (Abstract)

Alexander Mitev , Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-
Vineet Agarwal , Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-
Jin Sun , Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-
Janet Wang , Electrical and Computer Engineering Department, University of Arizona, Tucson, AZ - 85721. Tel: 520-
pp. 690-695

Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects (Abstract)

C.J. Akl , The Center for Adv. Comput. Studies, Louisiana at Lafayette Univ., LA
M.A. Bayoumi , The Center for Adv. Comput. Studies, Louisiana at Lafayette Univ., LA
pp. 696-701

Fast Buffered Delay Estimation Considering Process Variations (Abstract)

null Ting-Chi Wang , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu
null Tien-Ting Fang , Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu
pp. 702-707

Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect (Abstract)

Yehia Massoud , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Arthur Nieuwoudt , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
Mosin Mondal , Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005. Tel: 713-348-
pp. 708-713

Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores (Abstract)

Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Nara 630-01
Unni Chandran , Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,
Dan Zhao , Center for Advanced Computer Studies, University at Louisiana, Lafayette, Lafayette, LA 70504-4330,
pp. 714-719

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses (Abstract)

Tomokazu Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit
Fawnizu Azmadi Hussin , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science Cit
Alex Orailoglu , Computer Science and Engineering Department, University of California, San Diego, La Jolla, CA 92093
pp. 720-725

An Architecture for Combined Test Data Compression and Abort-on-Fail Test (Abstract)

Jon Persson , Embedded Systems Laboratory, Department of Computer and Information Science, Link?opings Universitet
Erik Larsson , Embedded Systems Laboratory, Department of Computer and Information Science, Link?opings Universitet
pp. 726-731

RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power (Abstract)

Chenguang Tong , Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0
Hao Fang , Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0
Xu Cheng , Micro Processor Research and Development Center of Peking University, Beijing, China, 100871. Tel: 0
pp. 732-737

Systematic Scan Reconfiguration (Abstract)

A.A. Al-Yamani , Comput. Eng., KFUPM, Dhahran
pp. 738-743

Configurable Multi-Processor Platforms for Next Generation Embedded Systems (Abstract)

Chris Rowen , Tensilica Inc., Santa Clara CA 95054. Tel: +1-408-327-7333, Fax: +1-408-986-8919, e-mail: rowen@tens
Grant Martin , Tensilica Inc., Santa Clara CA 95054. Tel: +1-408-327-7323, Fax: +1-408-986-8919, e-mail: gmartin@te
David Goodwin , Tensilica Inc., Santa Clara CA 95054. Tel: +1-123-456-7890, Fax: +1-408-986-8919, e-mail: goodwin@te
pp. 744-746

ARM MPCore; The streamlined and scalable ARM11 processor core (Abstract)

Kazuyuki Hirata , Business development, ARM K.K., Yokohama, Japan. Tel: +81-45-477-5173, Fax: +81-45-477-5261, e-mail:
John Goodacre , Processor product marketing, ARM, Cambridge, UK. Tel: +44-1223-400902, Fax: +44-1223-400410, e-mail:
pp. 747-748

Nomadik?: AMobile Multimedia Application Processor Platform (Abstract)

M. Paganini , Application Processor Div., STMicroelectronics, Grenoble
pp. 749-750

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach (Abstract)

null Xianlong Hong , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing
null Jin Shi , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing
null Yici Cai , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing
null Le Kang , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing
null Yi Zou , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beijing
pp. 751-756

Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks (Abstract)

David Blaauw , University of Michigan, Ann Arbor
Sanjay Pant , University of Michigan, Ann Arbor
pp. 757-762

Fast Placement Optimization of Power Supply Pads (Abstract)

null Yu Zhong , Dept. of Electr.&Comput. Eng., Illinois Univ., Urbana, IL
pp. 763-767

Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid (Abstract)

Yu Zhong , Dept. of Electrical and Computer Engineering, Univ. of Illinois, Urbana-Champaign, Urbana, IL, 61801
Martin D. F. Wong , Dept. of Electrical and Computer Engineering, Univ. of Illinois, Urbana-Champaign, Urbana, IL, 61801
pp. 768-773

A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms (Abstract)

Massoud Pedram , EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. pedram@usc.edu
Hanif Fatemi , EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. fatemi@usc.edu
Shahin Nazarian , EE-Systems Dept., University of Southern California, Los Angeles, CA 90089. shahin@usc.edu
pp. 774-779

Thermal-Aware 3D IC Placement Via Transformation (Abstract)

Yan Zhang , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:
Jason Cong , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:
Jie Wei , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:
Guojie Luo , Department of Computer Science, University of California, Los Angeles, Los Angeles, CA 90095. Email:
pp. 780-785

On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design (Abstract)

Chao-Hung Lu , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ch
Chien-Nan Jimmy Liu , Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, R.O.C. Email: ji
Hung-Ming Chen , E.E. Department and SoC Research Center, National Chiao Tung University, Hsinchu, Taiwan. Email: hmc
pp. 792-797

Voltage Island Generation under Performance Requirement for SoC Designs (Abstract)

Jr-Wei Chen , Department of Computer Science, National Tsing Hua Universtiy, Taiwan 300 R.O.C.
Wai-Kei Mak , Department of Computer Science, National Tsing Hua Universtiy, Taiwan 300 R.O.C.
pp. 798-803

Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign (Abstract)

Hung-Ming Chen , Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc
Ren-Jie Lee , Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc
Ming-Fang Lai , Department of Electronics Engineering and SoC Research Center, National Chiao Tung University, Hsinc
pp. 804-809

Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes (Abstract)

Zhuo Zhang , Dept. of ECE, University of Iowa, Iowa City, IA 52242. zhuzhang@engineering.uiowa.edu
Irith Pomeranz , School of ECE, Purdue University, Wet Lafayette, IN 47907. pomeranz@ecn.purdue.edu
Sudhakar M. Reddy , Dept. of ECE, University of Iowa, Iowa City, IA 52242. reddy@engineering.uiowa.edu
pp. 817-822

Fault Dictionary Size Reduction for Million-Gate Large Circuits (Abstract)

Yu-Ru Hong , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. yrhong.ee94g
Juinn-Dar Huang , Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. jdhuang@mail
pp. 829-834

Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation (Abstract)

Toshio Sugano , Elpida Memory, Inc. Technology&Development Office, 3-1-35 Minamihashimoto, Sagamihara, Kanagawa, 229
Hideki Kusamitsu , Yamaichi Electronics co., Ltd. 3-28-7 Nakaumagome, Otaku, Tokyo, 143-8515 Japan. e-mail: kusamitsu@y
Atsushi Hiraishi , Elpida Memory, Inc. Technology&Development Office, 3-1-35 Minamihashimoto, Sagamihara, Kanagawa, 229
pp. 841-845

Xbox360? Front Side Bus - A 21.6 GB/s End-to-End Interface Design (Abstract)

Steve Baumgartner , IBM Systems&Technology Group
David Siljenberg , IBM Systems&Technology Group
Jeff Johnson , Cadence Design Systems, Inc.
Trevor Timpane , IBM Systems&Technology Group
Tim Buchholtz , IBM Systems&Technology Group
Mark Maxson , IBM Systems&Technology Group
pp. 846-853

Design Consideration of 6.25 Gbps Signaling for High-Performance Server (Abstract)

Akira Hattori , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Weixin Gai , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Yasuo Hidaka , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Hideki Osone , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Yoichi Koyanagi , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Takeshi Horie , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
Jian Hong Jiang , Platform Innovation Group, Fujitsu Laboratories of America, Inc., 1240 East Arques Avenue, Sunnyvale
pp. 854-857

System Co-Design and Co-Analysis Approach to Implementing the XDR? Memory System of the Cell Broadband Engine? Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production (Abstract)

Ralf Schmitt , Signal Integrity, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: rsc
Wendemagegnehu Beyene , Signal Integrity, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: wbe
Scott Best , Architecture, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: sbest@r
Wai-Yeung Yip , Platform Solutions, Rambus Inc, Los Altos, CA 94022. Tel: 650-947-5000, Fax: 650-947-5001, e-mail: w
pp. 858-865

Flow Time Minimization under Energy Constraints (Abstract)

Hseuh-I Lu , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. hil@
Tei-Wei Kuo , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. ktw@
Kazuo Iwama , School of Informatics, Kyoto University, Yoshida-Honmachi, Kyoto, Japan. iwama@kuis.kyoto-u.ac.jp
Jian-Jia Chen , Department of Computer Science and Information Engineering, National Taiwan University, Taiwan. r900
pp. 866-871

Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost (Abstract)

B. Gorjiara , Dept. of Electr. Eng.&Comput. Sci., California Univ., Irvine, CA
pp. 872-877

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation (Abstract)

Hiroto Yasuura , System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847
Maziar Goudarzi , System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847
Tohru Ishihara , System LSI Research Center, Kyushu University, Fukuoka, Japan. Tel: +81-92-847-5193, Fax: +81-92-847
pp. 878-883

Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency (Abstract)

S. K. Nandy , CAD Laboratory, Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore,
Surendra G , CAD Laboratory, Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore,
Subhasis Banerjee , Diagnostics Engineering Group, Sun Microsystems, Bangalore, INDIA. E-mail: subhasis.banerjee@sun.com
pp. 884-889

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time (Abstract)

S. Parameswaran , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
J. Peddersen , Sch. of Comput. Sci.&Eng., New South Wales Univ., Sydney, NSW
pp. 890-895

Design Methodology for 2.4GHz Dual-Core Microprocessor (Abstract)

Akira Kanuma , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yoshitomo Ozeki , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yoshiyasu Tanamura , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hironobu Yoshino , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Kinya Ishizaka , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Ryoichi Yamashita , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hiroaki Komatsu , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Akihiro Yoshitake , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Yutaka Isoda , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hitoshi Yamanaka , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Noriyuki Ito , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. ito.noriyuki@jp.fujitsu
Takeshi Kono , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Ken-ichi Nabeya , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Masahiro Yanagida , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
Hiroyuki Sugiyama , Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan
pp. 896-901

An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools (Abstract)

null Fu-Ching Yang , Dept. of Comput. Sci.&Eng., National Sun Yat-sen Univ., Kaohsiung
null Ing-Jer Huang , Dept. of Comput. Sci.&Eng., National Sun Yat-sen Univ., Kaohsiung
pp. 902-907

A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications (Abstract)

Ahmet T. Erdogan , School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: Ah
Tughrul Arslan , School of Engineering and Electronic, The University of Edinburgh Edinburgh, EH9 3JL, UK. e-mail: T.
Zhenyu Liu , School of Engineering and Electronic, The University of Edinburgh, Edinburgh, EH9 3JL, UK. e-mail: z
pp. 908-913

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning (Abstract)

null Yuchun Ma , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beiijng
null Zhuoyuan Li , Dept. of Comput. Sci.&Technol., Tsinghua Univ., Beiijng
pp. 920-925

Multithreaded SAT Solving (Abstract)

Tobias Schubert , Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791
Matthew Lewis , Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791
Bernd Becker , Institute for Computer Science, Albert-Ludwigs-University of Freiburg, Georges-Koehler-Allee 51, 791
pp. 926-931

Trace Compaction using SAT-based Reachability Analysis (Abstract)

Sean Safarpour , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. sean@eecg
Andreas Veneris , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. veneris@e
Hratch Mangassarian , Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada. hratch@ee
pp. 932-937

Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets (Abstract)

S. Disch , Inst. of Comput. Sci., Albert-Ludwigs-Univ. Freiburg
C. Schollm , Inst. of Comput. Sci., Albert-Ludwigs-Univ. Freiburg
pp. 938-943

Fixing Design Errors with Counterexamples and Resynthesis (Abstract)

I.L. Markov , Michigan Univ., Ann Arbor, MI
null Kai-Hui Chang , Michigan Univ., Ann Arbor, MI
V. Bertacco , Michigan Univ., Ann Arbor, MI
pp. 944-949

Author Index (PDF)

pp. 951-958
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