The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (2007)
Yokohama
Jan. 23, 2007 to Jan. 26, 2007
ISBN: 1-4244-0629-3
pp: 678-683
H. Hassan , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
M. Anis , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
M. Elmasry , Electr.&Comput. Eng. Dept., Waterloo Univ., Ont.
ABSTRACT
A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.
INDEX TERMS
0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
CITATION
H. Hassan, M. Anis, M. Elmasry, "A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs", Asia and South Pacific Design Automation Conference, vol. 00, no. , pp. 678-683, 2007, doi:10.1109/ASPDAC.2007.358065
100 ms
(Ver 3.3 (11022016))