Asia and South Pacific Design Automation Conference (2007)
Jan. 23, 2007 to Jan. 26, 2007
Mongkol Ekpanyapong , Intel Corporation, Folsom, California, USA. firstname.lastname@example.org
Xin Zhao , Georgia Institute of Technology, Atlanta, Georgia, USA. email@example.com
Sung Kyu Lim , Georgia Institute of Technology, Atlanta, Georgia, USA. firstname.lastname@example.org
In this paper we present the Statistical Retiming-based Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing graph and identify the statistically critical paths under retiming, which are the paths with a high probability of becoming timing-critical after retiming. SRTA enables the designers to perform circuit optimization on these paths to reduce the probability of them becoming timing bottleneck if the circuit is retimed as a post-process. We provide a comparison among static timing analysis (= STA), statistical timing analysis (= SSTA), retiming-based timing analysis (= RTA), and our statistical retiming-based timing analysis (SRTA). Our results show that the placement optimization based on SRTA achieves the best performance results.
S. K. Lim, M. Ekpanyapong and X. Zhao, "An Efficient Computation of Statistically Critical Sequential Paths Under Retiming," 2007 Asia and South Pacific Design Automation Conference(ASP-DAC), Yokohama, 2007, pp. 547-552.