The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (2004)
Pacifico Yokohama, Yokohama, Japan
Jan. 27, 2004 to Jan. 30, 2004
ISBN: 0-7803-8175-0
TABLE OF CONTENTS

Keynote Addresses (PDF)

pp. vii-ix

List of Reviewers (PDF)

pp. xxvii-xxviii

On handling arbitrary rectilinear shape constraint (PDF)

X. Tang , Cadence Design Syst., San Jose, CA, USA
pp. 38-41

Fixed-outline floorplanning through evolutionary search (PDF)

Chang-Tzu Lin , Dept. of Inf. Eng. & Comput. Sci, Feng Chia Univ., Taichung, Taiwan
De-Sheng Chen , Dept. of Inf. Eng. & Comput. Sci, Feng Chia Univ., Taichung, Taiwan
Yi-Wen Wang , Dept. of Inf. Eng. & Comput. Sci, Feng Chia Univ., Taichung, Taiwan
pp. 42-44

Analog circuit behavioral modeling via wavelet collocation method with auto-companding (PDF)

Jian Wang , Microelectron. Dept., Fudan Univ., Shanghai, China
Jun Tao , Microelectron. Dept., Fudan Univ., Shanghai, China
Xuan Zeng , Microelectron. Dept., Fudan Univ., Shanghai, China
pp. 45-50

High-level modeling of continuous-time /spl Delta//spl Sigma/ A/D-converters using formal models (PDF)

E. Martens , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
G. Gielen , Dept. of Electr. Eng., Katholieke Univ., Leuven, Belgium
pp. 51-56

High-frequency noise in RF active CMOS mixers (PDF)

P. Heydari , Dept. of EECS, Univ. of California, Irvine, CA, USA
pp. 57-61

On mismatch in the deep sub-micron era-from physics to circuits (PDF)

R.O. Topaloglu , Comput. Sci. & Eng. Dept., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Comput. Sci. & Eng. Dept., California Univ., San Diego, La Jolla, CA, USA
pp. 62-67

Register binding and port assignment for multiplexer optimization (PDF)

D. Chen , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
J. Cong , Comput. Sci. Dept., California Univ., Los Angeles, CA, USA
pp. 68-73

Minimization of fractional wordlength on fixed-point conversion for high-level synthesis (PDF)

N. Doi , Graduate Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
pp. 80-85

A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline (PDF)

H.H. Najaf-Abadi , Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
pp. 86-91

TranGen: a SAT-based ATPG for path-oriented transition faults (PDF)

K. Yang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
K.-T. Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Li.-C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 92-97

Longest path selection for delay test under process variation (PDF)

X. Lu , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Z. Li , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 98-103
Session 1C - Modeling for Analog Circuits

On Mismatch in the Deep Sub-Micron Era - from Physics to Circuits (Abstract)

Rasit Onur Topaloglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 62-67
Session 1D - Behavioral Synthesis

Register Binding and Port Assignment for Multiplexer Optimization (Abstract)

Deming Chen , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 68-73

A Thread Partitioning Algorithm in Low Power High-Level Synthesis (Abstract)

Jumpei Uchida , Waseda University, Japan
Nozomu Togawa , The University of Kitakyushu, Japan; Waseda University, Japan
Masao Yanagisawa , Waseda University, Japan
Tatsuo Ohtsuki , Waseda University, Japan
pp. 74-79

Minimization of Fractional Wordlength on Fixed-Point Conversion for High-Level Synthesis (Abstract)

Nobuhiro Doi , Waseda University, Japan
Takashi Horiyama , Kyoto University, Japan
Masaki Nakanishi , Nara Institute of Science and Technology, Japan
Shinji Kimura , Waseda University, Japan
pp. 80-85
Session 1E - Delay Test and BIST

TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults (Abstract)

Kai Yang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
pp. 92-97

Longest Path Selection for Delay Test Under Process Variation (Abstract)

Xiang Lu , Texas A&M University, College Station, TX
Zhuo Li , Texas A&M University, College Station, TX
Wangqi Qiu , Texas A&M University, College Station, TX
D. M. H. Walker , Texas A&M University, College Station, TX
Weiping Shi , Texas A&M University, College Station, TX
pp. 98-103

Temperature-aware global placement (PDF)

B. Obermeier , Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany
F.M. Johannes , Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany
pp. 143-148

An integrated approach to timing-driven synthesis and placement of arithmetic circuits (PDF)

Keoncheol Shin , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
Taewhan Kim , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
pp. 155-158

Layer assignment for crosstalk risk minimization (PDF)

Di Wu , Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
pp. 159-162

NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO (PDF)

M. Chu , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
D.J. Allstot , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 169-174

Analytical expressions for phase noise eigenfunctions of LC oscillators (PDF)

P. Ghanta , Electr. & Comput. Eng. Dept., Arizona Univ., Tucson, AZ, USA
pp. 175-180

Timing optimization by replacing flip-flops to latches (PDF)

K. Yoshikawa , CAD Eng. Dept., NEC Corp., Tokyo, Japan
K. Kanamaru , CAD Eng. Dept., NEC Corp., Tokyo, Japan
pp. 186-191

An approach for reducing dynamic power consumption in synchronous sequential digital designs (PDF)

N. Chabini , Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada
pp. 198-204

Low power design using dual threshold voltage (PDF)

Yen-Te Ho , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Ting-Ting Hwang , Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 205-208

Technology mapping and packing for coarse-grained, anti-fuse based FPGAs (PDF)

Chang Woo Kang , Dept. of Electr. Eng. - Syst., Univ. of Southern California, Los Angeles, CA, USA
A. Iranli , Dept. of Electr. Eng. - Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. - Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 209-211

Efficient RT-level fault diagnosis methodology (PDF)

O. Sinanoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA
pp. 212-217

Design diagnosis using Boolean satisfiability (PDF)

A. Smith , Dept. of ECE, Toronto Univ., Ont., Canada
pp. 218-223

Test data compression technique using selective don't-care identification (PDF)

T. Hayashi , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
H. Yoshioka , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
T. Shinogi , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
H. Kita , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
H. Takase , Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
pp. 230-233

Re-configurable embedded core test protocol (PDF)

S. Wang , NEC Labs., Princeton, NJ, USA
S.T. Chakradhar , NEC Labs., Princeton, NJ, USA
pp. 234-237

Object-oriented modeling and synthesis of SystemC specifications (PDF)

C. Schulz-Key , Wilhelm-Schickard-Inst., Univ. of Tuebingen, Germany
M. Winterholer , Wilhelm-Schickard-Inst., Univ. of Tuebingen, Germany
T. Schweizer , Wilhelm-Schickard-Inst., Univ. of Tuebingen, Germany
T. Kuhn , Wilhelm-Schickard-Inst., Univ. of Tuebingen, Germany
W. Rosentiel , Wilhelm-Schickard-Inst., Univ. of Tuebingen, Germany
pp. 238-243

Application of UML for hardware design based on design process model (PDF)

R. Damasevicius , Software Eng. Dept., Kaunas Univ. of Technol., Lithuania
V. Stuikys , Software Eng. Dept., Kaunas Univ. of Technol., Lithuania
pp. 244-249

A cosynthesis algorithm for application specific processors with heterogeneous datapaths (PDF)

Y. Miyaoka , Dept. of Electron., Inf. & Commun. Eng., Waseda Univ., Tokyo, Japan
pp. 250-255

Design methodology for SoC architectures based on reusable virtual cores (PDF)

M. Muraoka , Semicon. Technol. Acad. Res. Center, Yokohama, Japan
H. Nishi , Semicon. Technol. Acad. Res. Center, Yokohama, Japan
R.K. Morizawa , Semicon. Technol. Acad. Res. Center, Yokohama, Japan
H. Yokota , Semicon. Technol. Acad. Res. Center, Yokohama, Japan
H. Hamada , Semicon. Technol. Acad. Res. Center, Yokohama, Japan
pp. 256-262

A mulitple level network approach for clock skew minimization with process variations (PDF)

M. Mori , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Hongyu Chen , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
B. Yao , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Chung-Kuan Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 263-268

Layout techniques for on-chip interconnect inductance reduction (PDF)

Shang-Wei Tu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 269-273

Piecewise quadratic waveform matching with successive chord iteration (PDF)

Z. Wang , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
J. Zhu , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 274-279

Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming (PDF)

Hsu-Wei Huang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Cheng-Yeh Wang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 280-283

Adaptive supply voltage technique for low swing interconnects (PDF)

W. Jeong , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
B.C. Paul , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Kaushik Roy , Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 284-287

Jitter spectral extraction for multi-gigahertz signal (PDF)

C.-K. Ong , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
D. Hong , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
K.-T. Cheng , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
L.-C. Wang , Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 298-303

A 35 dB-linear exponential function generator for VGA and AGC applications (PDF)

Quoc-Hoang Duong , Inf. & Commun. Univ., Daejeon, South Korea
Sang-Gug Lee , Inf. & Commun. Univ., Daejeon, South Korea
pp. 304-309

A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique (PDF)

S.C. Li , National Yunlin University of Seience and Technology
pp. 307-309

Efficient translation of Boolean formulas to CNF in formal verification of microprocessors (PDF)

M.N. Velev , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 310-315

Using positive equality to prove liveness for pipelined microprocessors (PDF)

M.N. Velev , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 316-321

On deriving equivalent architecture model from system specification (PDF)

S. Abdi , Center for Embedded Comput. Syst., UC Irvine, CA, USA
D. Gajski , Center for Embedded Comput. Syst., UC Irvine, CA, USA
pp. 322-327

On compliance test of on-chip bus for SOC (PDF)

Hue-Min Lin , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chia-Chih Yen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Che-Hua Shih , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jing-Yang Jou , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 328-333
Session 3C - Analog Design and Evaluation

A 35 dB-Linear Exponential Function Generator for VGA And AGC Applications (Abstract)

Quoc-Hoang Duong , Information and Communication University, South Korea
Sang-Gug Lee , Information and Communication University, South Korea
pp. 304-306

Open architecture test system: not why but when! (PDF)

S. Chakradhar , NEC Laboratories America
pp. 337-340

Opportunities with the open architecture test system (PDF)

T. Tada , Tokushima Bunri University
pp. 343-348

A place and route aware buffered Steiner tree construction (PDF)

C.N. Sze , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
J. Hu , Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
pp. 355-360

Modeling of coplanar waveguide for buffered clock tree (PDF)

J. Chen , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 367-372

Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures (PDF)

Kugan Vivekanandarajah , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
Thambipillai Srikanthan , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
Saurav Bhattacharyya , Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
pp. 373-379

Power-performance trade-off using pipeline delays (PDF)

G. Surendra , CAD Lab., Indian Inst. of Sci., Bangalore, India
Subhasis Banerjee , CAD Lab., Indian Inst. of Sci., Bangalore, India
S.K. Nandy , CAD Lab., Indian Inst. of Sci., Bangalore, India
pp. 384-386

Exploiting program execution phases to trade power and performance for media workload (PDF)

Subhasis Banerjee , Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
G. Surendra , Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
S.K. Nandy , Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
pp. 387-389

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting (PDF)

N. Jangkrajarng , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Sambuddha Bhattacharya , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Roy Hartono , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 394-399

Hierarchical extraction and verification of symmetry constraints for analog layout automation (PDF)

Sambuddha Bhattacharya , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
N. Jangkrajarng , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Roy Hartono , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C.-J.R. Shi , Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 400-405

Multilevel placement with circuit schema based clustering in analog IC layouts (PDF)

T. Nojima , Syst. Dev. Dept., SII EDA Technologies Inc., Fukuoka, Japan
X. Zhu , Syst. Dev. Dept., SII EDA Technologies Inc., Fukuoka, Japan
pp. 406-411

Model checking on state transition diagram (PDF)

Batsayan Das , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
pp. 412-417

Efficient reachability checking using sequential SAT (PDF)

G. Parthasarathy , Dept. of ECE, California Univ., Santa Barbara, CA, USA
M.K. Iyer , Dept. of ECE, California Univ., Santa Barbara, CA, USA
K.T. Cheng , Dept. of ECE, California Univ., Santa Barbara, CA, USA
L.C. Wang , Dept. of ECE, California Univ., Santa Barbara, CA, USA
pp. 418-423

Exploiting state encoding for invariant generation in induction-based property checking (PDF)

M. Wedler , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
D. Stoffel , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
W. Kunz , Dept. of Electr. & Comput. Eng., Kaiserslautern Univ., Germany
pp. 424-429

Tradeoff routing resource, runtime and quality in buffered routing (PDF)

X. Tang , Cadence Design Syst., San Jose, CA, USA
pp. 430-433

Practical methodology of post-layout gate sizing for 15% more power saving (PDF)

N. Miura , Dept. of Electron. & Electr. Eng., Keio Univ., Japan
pp. 434-437

Interconnect design methods for memory design (PDF)

C. Hwang , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
M. Pedram , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 438-443

Optimal planning for mesh-based power distribution (PDF)

H. Chen , Dept. of Comput. Sci. & Eng., California Univ., San Diego, USA
C.-K. Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, USA
A.B. Kahng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, USA
Q. Wang , Dept. of Comput. Sci. & Eng., California Univ., San Diego, USA
pp. 444-449

2.5D system integration: a design driven system implementation schema (PDF)

Y. Deng , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 450-455

An HMAC processor with integrated SHA-1 and MD5 algorithms (PDF)

Mao-Yin Wang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Pin Su , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Chih-Tsun Huang , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Cheng-Wen Wu , Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
pp. 456-458

Design methodology for IRA codes (PDF)

F. Kienle , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
N. Wehn , Microelectron. Syst. Design Res. Group, Kaiserslautern Univ., Germany
pp. 459-462

Embedded software generation from system level design languages (PDF)

H. Yu , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
R. Domer , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
D. Gajski , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 463-468

Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model (PDF)

A. Bouchhima , System-Level Synthesis Group, TIMA Lab., Grenoble, France
S. Yoo , System-Level Synthesis Group, TIMA Lab., Grenoble, France
A. Jerraya , System-Level Synthesis Group, TIMA Lab., Grenoble, France
pp. 469-474

Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA) (PDF)

Aviral Shrivasta , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
Nikil Dutt , Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA
pp. 475-477

Memory access driven storage assignment for variables in embedded system design (PDF)

Yoonseo Choi , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
Taewhan Kim , Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
pp. 478-481

MOSFET modeling for RF-CMOS design (PDF)

M. Miura-Mattausch , Adv. Sci. of Matter, Hiroshima Univ., Japan
pp. 482-490

RF design methodologies bridging system-IC-module design (PDF)

R.A. Mullen , Cadence Design Syst. Inc., San Jose, CA, USA
pp. 491-498

Hierarchical random-walk algorithms for power grid analysis (PDF)

H. Qian , Dept. of Electr & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
S.S. Sapatnekar , Dept. of Electr & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
pp. 499-504

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery (PDF)

Jingjing Fu , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Zuying Luo , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Xianlong Hong , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Yici Cai , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
pp. 505-510

Large-scale linear circuit simulation with an inversed inductance matrix (PDF)

C. Mizuta , Math. Syst. Inc., Tokyo, Japan
J. Iwai , Math. Syst. Inc., Tokyo, Japan
K. Machida , Math. Syst. Inc., Tokyo, Japan
pp. 511-516

Design of real-time VGA 3-D image sensor using mixed-signal techniques (PDF)

Y. Oike , Dept. of Electron. Eng., Tokyo Univ., Japan
M. Ikeda , Dept. of Electron. Eng., Tokyo Univ., Japan
K. Asada , Dept. of Electron. Eng., Tokyo Univ., Japan
pp. 523-524

A bandwidth and memory efficient MPEG-4 shape encoder (PDF)

Kun-Bin Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Nelson Yen-Chung Chang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Hao-Yun Chin , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Hui-Cheng Hsu , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chein-Wei Jen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 525-526

A sub-mW MPEG-4 motion estimation processor core for mobile video application (PDF)

Y. Kuroda , Fac. of Eng., Kanazawa Univ., Japan
J. Miyakoshi , Fac. of Eng., Kanazawa Univ., Japan
M. Miyama , Fac. of Eng., Kanazawa Univ., Japan
K. Imamura , Fac. of Eng., Kanazawa Univ., Japan
H. Hashimoto , Fac. of Eng., Kanazawa Univ., Japan
M. Yoshimoto , Fac. of Eng., Kanazawa Univ., Japan
pp. 527-528

Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision (PDF)

K. Nishio , Dept. of Electr. & Electron. Eng., Toyohashi Univ. of Technol., Japan
H. Yonezu , Dept. of Electr. & Electron. Eng., Toyohashi Univ. of Technol., Japan
S. Sawa , Dept. of Electr. & Electron. Eng., Toyohashi Univ. of Technol., Japan
Y. Furukawa , Dept. of Electr. & Electron. Eng., Toyohashi Univ. of Technol., Japan
pp. 529-530

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node (PDF)

T. Morimoto , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Y. Harada , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
T. Koide , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
H.J. Mattausch , Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
pp. 531-532

A high efficiency 0.5W BTL class-D audio amplifier with RWDM technique (PDF)

S.C. Li , National Yunlin University of Science and Technology
pp. 535-536

A closed caption TV microcontroller (PDF)

E. Leelarasmee , Chulalongkorn University
pp. 573-574

Design and implementation of a secret key steganographic micro-architecture employing FPGA (PDF)

H.A. Farouk , Arab Academy for Science, Technology and Maritime Transport
pp. 577-578
Session 6C - (Special Session) Presentation + Poster Disscussion: University Design Contest

Improvement of Saturation Characteristics of a Frequency-Demodulation CMOS Image Sensor (PDF)

Jun Ohta , Nara Institute of Science and Technology (NAIST), Japan
Koichi Yamamoto , Nara Institute of Science and Technology (NAIST), Japan
Yu Oya , Nara Institute of Science and Technology (NAIST), Japan
Keiichiro Kagawa , Nara Institute of Science and Technology (NAIST), Japan
Takashi Tokuda , Nara Institute of Science and Technology (NAIST), Japan
Masahiro Nunoshita , Nara Institute of Science and Technology (NAIST), Japan
pp. 575-576

Verification of timed circuits with symbolic delays (PDF)

R. Clariso , Universitat Politecnica de Catalunya
pp. 628-633
Session 6D - Novel Techniques in Logic Synthesis

Transduction Method for Design of Logic Cell Structure (Abstract)

Katsunori Tanaka , Kyoto University, Japan
Yahiko Kambayashi , Kyoto University, Japan
pp. 600-603
Session 7B - Buffer Planning

Integrating Buffer Planning with Floorplanning for Simultaneous Multi-Objective Optimization (Abstract)

Yi-Hui Cheng , Synopsys Inc., Taipei, Taiwan
Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
pp. 624-627
Session 7D - Task Scheduling with DVS

Minimizing Energy Consumption of Hard Real-Time Systems with Simultaneous Tasks Scheduling and Voltage Assignment Using Statistical Data (Abstract)

Lap-Fai Leung , Hong Kong University of Science and Technology
Chi-Ying Tsui , Hong Kong University of Science and Technology
Wing-Hung Ki , Hong Kong University of Science and Technology
pp. 663-665
Session 8B - Interconnect and ESD Extraction

A Mixed-Mode Extraction Flow for High Performance Microprocessors (Abstract)

Tao Jiang , Motorola Inc., Austin, TX
Eric Pettus , Motorola Inc., Austin, TX
Daksh Lehther , Motorola Inc., Austin, TX
pp. 697-701

Minimization of memory size for heterogeneous MDDs (PDF)

S. Nagayama , Kyushu Institute of Technology
pp. 872-875
Session 10C - Expressions for Boolean Functions

Minimization of Memory Size for Heterogeneous MDDs (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology
Shinobu Nagayama , Kyushu Institute of Technology
pp. 871-874
Session 10C - Expressions for Boolean Functions

ShatterPB: Symmetry-Breaking for Pseudo-Boolean Formulas (Abstract)

Fadi A. Aloul , American University in Dubai
Arathi Ramani , University of Michigan, Ann Arbor
Igor L. Markov , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
pp. 883-886

[Back cover - Blank] (PDF)

pp. 919-920
Session 10D - Semi-Custom Techniques in System Design

Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor (Abstract)

Yiran Chen , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
pp. 893-898

High-Level Area and Power-Up Current Estimation Considering Rich Cell Library (Abstract)

Fei Li , University of California, Los Angeles, CA
Lei He , University of California, Los Angeles, CA
Joseph M. Basile , Intel Corporation, Santa Clara, CA
Rakesh J. Patel , Intel Corporation, Santa Clara, CA
Hema Ramamurthy , Intel Corporation, Santa Clara, CA
pp. 899-904

Author Index (PDF)

pp. 905-911
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