The Community for Technology Leaders
Asia and South Pacific Design Automation Conference (2004)
Pacifico Yokohama, Yokohama, Japan
Jan. 27, 2004 to Jan. 30, 2004
ISBN: 0-7803-8175-0
TABLE OF CONTENTS

Keynote Addresses (PDF)

pp. vii-ix

List of Reviewers (PDF)

pp. xxvii-xxviii
Keynote Address
Session 1A - (Special Session) Invited Talks: Selected European Activities in SoC Low Power Design Methodologies and Research Networking

Fast, Predictable and Low Energy Memory References through Architecture-Aware Compilation (Abstract)

Manish Verma , University of Dortmund, Germany
Peter Marwedel , University of Dortmund, Germany
Lars Wehmeyer , University of Dortmund, Germany
Urs Helmig , University of Dortmund, Germany
Stefan Steinke , Kostal GmbH & Co KG, Lüdenscheid, Germany
pp. 4-11
Session 1B - Floorplanning

Abstraction and Optimization of Consistent Floorplanning with Pillar Block Constraints (Abstract)

Ning Fu , University of Kitakyushu, Japan
Yoji Kajitani , University of Kitakyushu, Japan
Shigetoshi Nakatake , University of Kitakyushu, Japan
Yasuhiro Takashima , University of Kitakyushu, Japan
pp. 19-24

Space-Planning: Placement of Modules with Controlled Empty Area by Single-Sequence (Abstract)

Xuliang Zhang , SII EDA Techonologies Inc., Kitakyushu, Japan
Yoji Kajitani , The University of Kitakyushu, Japan
pp. 25-30

Layer Assignment for Reliable System-on-Package (Abstract)

Jacob R. Minz , Georgia Institute of Technology, Atlanta, GA
Sung Kyu Lim , Georgia Institute of Technology, Atlanta, GA
pp. 31-37

On Handling Arbitrary Rectilinear Shape Constraint (Abstract)

Martin D.F. Wong , University of Illinois, Urbana, IL
Xiaoping Tang , Cadence Design Systems, San Jose, CA
pp. 38-41

Robust Fixed-Outline Floorplanning Through Evolutionary Search (Abstract)

Yi-Wen Wang , Feng Chia University, Taichung, Taiwan
Chang-Tzu Lin , Feng Chia University, Taichung, Taiwan
De-Sheng Chen , Feng Chia University, Taichung, Taiwan
pp. 42-44
Session 1C - Modeling for Analog Circuits

Analog Circuit Behavioral Modeling via Wavelet Collocation Method with Auto-Companding (Abstract)

Jian Wang , Fudan University, China P.R.
Jun Tao , Fudan University, China P.R.
Charles Chiang , Synopsys Inc., Mountain View, CA
Dian Zhou , University of Texas at Dallas
Xuan Zeng , Fudan University, China P.R.
pp. 45-50

High-Level Modeling of Continuous-Time ∆Σ A/D-Converters Using Formal Models (Abstract)

Ewout Martens , Katholieke Universiteit Leuven, Belgium
Georges Gielen , Katholieke Universiteit Leuven, Belgium
pp. 51-56

High-Frequency Noise in RF Active CMOS Mixers (Abstract)

Payam Heydari , University of California, Irvine
pp. 57-60

On Mismatch in the Deep Sub-Micron Era - from Physics to Circuits (Abstract)

Rasit Onur Topaloglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 62-67
Session 1D - Behavioral Synthesis

Register Binding and Port Assignment for Multiplexer Optimization (Abstract)

Deming Chen , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 68-73

A Thread Partitioning Algorithm in Low Power High-Level Synthesis (Abstract)

Tatsuo Ohtsuki , Waseda University, Japan
Masao Yanagisawa , Waseda University, Japan
Jumpei Uchida , Waseda University, Japan
Nozomu Togawa , The University of Kitakyushu, Japan; Waseda University, Japan
pp. 74-79

Minimization of Fractional Wordlength on Fixed-Point Conversion for High-Level Synthesis (Abstract)

Takashi Horiyama , Kyoto University, Japan
Masaki Nakanishi , Nara Institute of Science and Technology, Japan
Nobuhiro Doi , Waseda University, Japan
Shinji Kimura , Waseda University, Japan
pp. 80-85
Session 1E - Delay Test and BIST

TranGen: A SAT-Based ATPG for Path-Oriented Transition Faults (Abstract)

Kai Yang , University of California, Santa Barbara
Li-C. Wang , University of California, Santa Barbara
Kwang-Ting Cheng , University of California, Santa Barbara
pp. 92-97

Longest Path Selection for Delay Test Under Process Variation (Abstract)

Wangqi Qiu , Texas A&M University, College Station, TX
Weiping Shi , Texas A&M University, College Station, TX
D. M. H. Walker , Texas A&M University, College Station, TX
Xiang Lu , Texas A&M University, College Station, TX
Zhuo Li , Texas A&M University, College Station, TX
pp. 98-103

SRAM Delay Fault Modeling and Test Algorithm Development (Abstract)

Yan-Ting Lai , National Tsing Hua University, Hsinchu, Taiwan
Rei-Fu Huang , National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu , National Tsing Hua University, Hsinchu, Taiwan
Yung-Fa Chou , National Tsing Hua University, Hsinchu, Taiwan
pp. 104-109

An Efficient Design of Non-Linear CA Based PRPG for VLSI Circuit Testing (Abstract)

Biplab K. Sikdar , B. E. College (a Deemed University), Howrah, India
Sukanta Das , B. E. College (a Deemed University), Howrah, India
Subhayan Sen , B. E. College (a Deemed University), Howrah, India
Debdas Dey , B. E. College (a Deemed University), Howrah, India
P. Pal Chaudhuri , B. E. College (a Deemed University), Howrah, India
pp. 110-112

Combinatorial Group Testing Methods for the BIST Diagnosis Problem (Abstract)

Andrew B. Kahng , University of CA, San Diego
Sherief Reda , University of CA, San Diego
pp. 113-116
Session 2A - (Special Session) Embedded Tutorial + Reguler Session: Embedded System Applications

Toward Mobile Phone Linux (Abstract)

Yukikazu Nakamoto , NEC Network Development Laboratories, Japan
pp. 117-124

Power Control of CDMA Systems with Successive Interference Cancellation Using the Knowledge of Battery Power Capacity (Abstract)

Yan Wang , ASTRI, Hong Kong
Wai Ho Mow , The Hong Kong University of Science & Technology, Hong Kong
Chi-Ying Tsui , The Hong Kong University of Science & Technology, Hong Kong
Roger S. Cheng , The Hong Kong University of Science & Technology, Hong Kong
pp. 125-130
Session 2B - Placement

Performance-Driven Global Placement via Adaptive Network Characterization (Abstract)

Sung Kyu Lim , Georgia Institute of Technology
Mongkol Ekpanyapong , Georgia Institute of Technology
pp. 137-142

Temperature-Aware Global Placement (Abstract)

Frank M. Johannes , Technical University of Munich
Bernd Obermeier , Technical University of Munich
pp. 143-148

High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability (Abstract)

Kunihiro Asada , University of Tokyo, Japan
Tetsuya Iizuka , University of Tokyo, Japan
Makoto Ikeda , University of Tokyo, Japan
pp. 149-154

An Integrated Approach to Timing-Driven Synthesis and Placement of Arithmetic Circuits (Abstract)

Keoncheol Shin , Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim , Korea Advanced Institute of Science and Technology, KOREA
pp. 155-158

Layer Assignment for Crosstalk Risk Minimization (Abstract)

Jiang Hu , Texas A&M University, College Station, TX
Di Wu , Texas A&M University, College Station, TX
Rabi Mahapatra , Texas A&M University, College Station, TX
Min Zhao , Advanced Tools Group, Motorola Inc., Austin, TX
pp. 159-162
Session 2C - RF Design Methodology

CrtSmile: A CAD Tool for CMOS RF Transistor Substrate Modeling Incorporating Layout Effects (Abstract)

Zhao Li , University of Washington, Seattle, WA
Richard Shi , University of Washington, Seattle, WA
Ravikanth Suravarapu , Oregon State University, Corvallis, OR
Roy Hartono , University of Washington, Seattle, WA
Karti Mayaram , Oregon State University, Corvallis, OR
Sambuddha Bhattacharya , University of Washington, Seattle, WA
pp. 163-168

NSGA-Based Parasitic-Aware Optimization of a 5GHz Low-Noise VCO (Abstract)

Jeffrey M. Huard , National Semiconductor Corporation, Federal Way, WA
Min Chu , University of Washington, Seattle, WA
Kim Y. Wong , National Semiconductor Corporation, Federal Way, WA
David J. Allstot , University of Washington, Seattle, WA
pp. 169-173

Analytical Expressions for Phase Noise Eigenfunctions of LC Oscillators (Abstract)

Zheng Li , University of Minnesota, USA
Praveen Ghanta , University of Arizona, USA
Jaijeet Roychowdhury , University of Minnesota, USA
pp. 175-180

Analysis of MOS Cross-Coupled LC-Tank Oscillators using Short-Channel Device Equations (Abstract)

Mohammad M. Mansour , American University of Beirut, Beirut, Lebanon
Amit Mehrotra , University of Illinois at Urbana-Champaign
Makram M. Mansour , Berkeley Design Automation, Santa Clara, CA
pp. 181-185
Session 2D - Practical Issues in Logic Synthesis

Timing Optimization by Replacing Flip-Flops to Latches (Abstract)

Shigeto Inui , NEC Corp., Fuchu, Tokyo
Ko Yoshikawa , NEC Corp., Fuchu, Tokyo
Takeshi Yoshimura , Waseda University, Japan
Yuici Nakamura , NEC Corp., Fuchu, Tokyo
Yasuhiko Hagihara , NEC Corp., Fuchu, Tokyo
Keisuke Kanamaru , NEC Corp., Fuchu, Tokyo
pp. 186-191

Enhancing the Performance of Multi-Cycle Path Analysis in an Industrial Setting (Abstract)

Hiroyuki Higuchi , Fujitsu Laboratories Ltd. / Kyushu University
Yusuke Matsunaga , Kyushu University
pp. 192-198

An Approach for Reducing Dynamic Power Consumption in Synchronous Sequential Digital Designs (Abstract)

Noureddine Chabini , Royal Military College of Canada
Wayne Wolf , Princeton University, NJ, USA
pp. 198-204

Low Power Design Using Dual Threshold Voltage (Abstract)

Yen-Te Ho , National Tsing Hua University HsinChu, Taiwan
Ting-Ting Hwang , National Tsing Hua University HsinChu, Taiwan
pp. 205-208

Technology Mapping and Packing for Coarse-Grained, Anti-Fuse Based FPGAs (Abstract)

Ali Iranli , University of Southern California, Los Angeles
Chang Woo Kang , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 209-211
Session 2E - Effective Test and Diagnosis

Efficient RT-level Fault Diagnosis Methodology (Abstract)

Ozgur Sinanoglu , University of California, San Diego
Alex Orailoglu , University of California, San Diego
pp. 212-217

Design Diagnosis Using Boolean Satisfiability (Abstract)

Andreas Veneris , University of Toronto, Canada
Anastasios Viglas , University of Toronto, Canada
Alexander Smith , University of Toronto, Canada
pp. 218-223

Testable Design of GRM Network with EXOR-Tree for Detecting Stuck-at and Bridging Faults (Abstract)

Hafizur Rahaman , B. E. College (D. U.), India
Debesh K. Das , Jadavpur University, India
Bhargab B. Bhattacharya , Indian Statistical Institute, India
pp. 224-229

Test Data Compression Technique Using Selective Don't-Care Identification (Abstract)

Haruhiko Takase , Mie University, Japan
Tsuyoshi Shinogi , Mie University, Japan
Hidehiko Kita , Mie University, Japan
Terumine Hayashi , Mie University, Japan
Haruna Yoshioka , Mie University, Japan
pp. 230-233

Re-configurable Embedded Core Test Protocol (Abstract)

Srimat T. Chakradhar , NEC Labs., America
Seongmoon Wang , NEC Labs., America
Balakrishnan Kedarnath , University of Texas at Austin
pp. 234-237
Session 3A - System-Level Design Methodology

Object-Oriented Modeling and Synthesis of SystemC Specifications (Abstract)

C. Schulz-Key , University of Tuebingen, Germany
T. Schweizer , University of Tuebingen, Germany
T. Kuhn , University of Tuebingen, Germany
M. Winterholer , University of Tuebingen, Germany
W. Rosenstiel , University of Tuebingen, Germany
pp. 238-243

Application of UML for Hardware Design Based on Design Process Model (Abstract)

Vytautas Stuikys , Kaunas University of Technology, Lithuania
Robertas Damasevicius , Kaunas University of Technology, Lithuania
pp. 244-249

A Cosynthesis Algorithm for Application Specific Processors with Heterogeneous Datapaths (Abstract)

Tatsuo Ohtsuki , Waseda University
Masao Yanagisawa , Waseda University
Nozomu Togawa , The University of Kitakyushu
Yuichiro Miyaoka , Waseda University
pp. 250-255

Design Methodology for SoC Architectures based on Reusable Virtual Cores (Abstract)

Hiroaki Nishi , Semiconductor Technology Academic Research Center (STARC), Japan
Michiaki Muraoka , Semiconductor Technology Academic Research Center (STARC), Japan
Hideaki Yokota , Semiconductor Technology Academic Research Center (STARC), Japan
Rafael K. Morizawa , Semiconductor Technology Academic Research Center (STARC), Japan
Hideyuki Hamada , Semiconductor Technology Academic Research Center (STARC), Japan
pp. 256-262
Session 3B - Advanced Design and Modeling Techniques

A Mulitple Level Network Approach for Clock Skew Minimization with Process Variations (Abstract)

Makoto Mori , University of California, San Diego
Bo Yao , University of California, San Diego
Hongyu Chen , University of California, San Diego
Chung-Kuan Cheng , University of California, San Diego
pp. 263-268

Layout Techniques for On-Chip Interconnect Inductance Reduction (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
Shang-Wei Tu , National Chiao Tung University, Hsinchu, Taiwan
Jing-Yang Jou , National Chiao Tung University, Hsinchu, Taiwan
pp. 269-273

Piecewise Quadratic Waveform Matching with Successive Chord Iteration (Abstract)

Zhong Wang , University of Toronto, Ontario, Canada
Jianwen Zhu , University of Toronto, Ontario, Canada
pp. 274-279

Optimal Design of High Fan-In Multiplexers via Mixed-Integer Nonlinear Programming (Abstract)

Cheng-Yeh Wang , National Chiao Tung University, Taiwan
Hsu-Wei Huang , National Chiao Tung University, Taiwan
Jing-Yang Jou , National Chiao Tung University, Taiwan
pp. 280-283

Adaptive Supply Voltage Technique for Low Swing Interconnects (Abstract)

Bipul Chandra Paul , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
Woopyo Jeong , Purdue University, West Lafayette, IN
pp. 284-287
Session 3C - Analog Design and Evaluation

A Large-Current-Output Boosted Voltage Generator with Non-Overlapping Clock Control for Sub-1-V Memory Applications (Abstract)

Dong Myeong Kim , Kookmin University, Seoul, Korea
Young-Hee Kim , Changwon National University, Changwon-Si, Korea
Jin-Hong Ahn , Hynix Semiconductor Inc., Ichon-Si, Korea
Kyeong-Sik Min , Kookmin University, Seoul, Korea
Daejeong Kim , Kookmin University, Seoul, Korea
pp. 288-291

Effects of Noise and Nonlinearity on the Calibration of a Non-Binary Capacitor Array in a Successive Approximation Analog-to-Digital Converter (Abstract)

Jacob Abraham , The University of Texas at Austin
Shouli Yan , The University of Texas at Austin
Jianhua Gan , Cirrus Logic, Inc., Austin, TX
pp. 292-297

Jitter Spectral Extraction for Multi-Gigahertz Signal (Abstract)

Li-C Wang , University of California, Santa Barbara
Dongwoo Hong , University of California, Santa Barbara
Kwang-Ting (Tim) Cheng , University of California, Santa Barbara
Chee-Kian Ong , University of California, Santa Barbara
pp. 298-303

A 35 dB-Linear Exponential Function Generator for VGA And AGC Applications (Abstract)

Sang-Gug Lee , Information and Communication University, South Korea
Quoc-Hoang Duong , Information and Communication University, South Korea
pp. 304-306

A High Efficiency 0.5W BTL Class-D Audio Amplifier with RWDM Technique (Abstract)

Vincent Chia-Chang Lin , Etrend Electronics, Inc.
Simon C. Li , National Yunlin University of Science and Technology
pp. 307-309
Session 3D - System Design Verification

Using Positive Equality to Prove Liveness for Pipelined Microprocessors (Abstract)

Miroslav N. Velev , Carnegie Mellon University, Pittsburgh, PA
pp. 316-321

On Compliance Test of On-Chip Bus for SOC (Abstract)

Che-Hua Shih , National Chiao Tung University, Taiwan
Chia-Chih Yen , National Chiao Tung University, Taiwan
Hue-Min Lin , National Chiao Tung University, Taiwan
Jing-Yang Jou , National Chiao Tung University, Taiwan
pp. 328-333
Session 3E - (Special Session) Panel Discussion: Opportunities with the Open Architecture Test System

New Opportunities with the Open Architecture Test System (PDF)

Rochit Rajsuman , Advantest America R&D Center, Santa Clara, CA
pp. 335

Open Architecture Test System: Not Why but When! (Abstract)

Srimat Chakradhar , NEC Laboratories America, Princeton, NJ
pp. 337-340

"Signal Integrity Analysis in the Open Architecture" (PDF)

Dennis M. Petrich , Wavecrest Corporation, Eden Prairie, MN
pp. 342

Opportunities with the Open Architecture Test System (PDF)

Tetsuo Tada , Tokushima Bunri University, Japan
pp. 343
Session 4A - (Special Session) Invited Talks: C-Based Design Examples

Using C Based Logic Synthesis to Bridge the Productivity Gap (Abstract)

Stephen Chappell , Celoxica Ltd
Alex Wilson , Celoxica Ltd
Chris Sullivan , Celoxica Ltd
pp. 349-354
Session 4B - Buffered Tree Construction

A Place and Route Aware Buffered Steiner Tree Construction (Abstract)

C. N. Sze , Texas A&M University, College Station, TX
Charles J. Alpert , IBM Austin Research Lab, Austin, TX
Jiang Hu , Texas A&M University, College Station, TX
pp. 355-360

An Efficient Routing Tree Construction Algorithm with Buffer Insertion, Wire Sizing and Obstacle Considerations (Abstract)

Sampath Dechu , Micron Technology Inc., Boise, ID
Zion Cien Shen , Iowa State University, Ames, IA
Chris C. N. Chu , Iowa State University, Ames, IA
pp. 361-366

Modeling of Coplanar Waveguide for Buffered Clock Tree (Abstract)

Jun Chen , University of California, Los Angeles
Lei He , University of California, Los Angeles
pp. 367-372
Session 4C - Power-Aware Approach for Microprocessor Design

Decode Filter Cache for Energy Efficient Instruction Cache Hierarchy in Super Scalar Architectures (Abstract)

Kugan Vivekanandarajah , Nanyang Technological University, Singapore
Thambipillai Srikanthan , Nanyang Technological University, Singapore
Saurav Bhattacharyya , Nanyang Technological University, Singapore
pp. 373-379

Mixed-Clock Issue Queue Design for Energy Aware, High-Performance Cores (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
Venkata Syam P. Rapaka , Mentor Graphics Corp., Wilsonville, OR
Emil Talpes , Carnegie Mellon University, Pittsburgh, PA
pp. 380-383

Power-Performance Trade-Off using Pipeline Delays (Abstract)

G. Surendra , Indian Institute of Science, Bangalore, India
Subhasis Banerjee , Indian Institute of Science, Bangalore, India
S. K. Nandy , Indian Institute of Science, Bangalore, India
pp. 384-386

Exploiting Program Execution Phases to Trade Power and Performance for Media Workload (Abstract)

G. Surendra , Indian Institute of Science, Bangalore, India
S. K. Nandy , Indian Institute of Science, Bangalore, India
Subhasis Banerjee , Indian Institute of Science, Bangalore, India
pp. 387-389

LPRAM: A Low Power DRAM with Testability (Abstract)

Subhasis Bhattacharjee , University of Bristol, UK
Dhiraj K. Pradhan , University of Bristol, UK
pp. 390-393
Session 4D - Analog Layout Techniques

Multiple Specifications Radio-Frequency Integrated Circuit Design with Automatic Template-Driven Layout Retargeting (Abstract)

Sambuddha Bhattacharya , University of Washington, Seattle, WA
Roy Hartono , University of Washington, Seattle, WA
Nuttorn Jangkrajarng , University of Washington, Seattle, WA
C-J. Richard Shi , University of Washington, Seattle, WA
pp. 394-399

Hierarchical Extraction and Verification of Symmetry Constraints for Analog Layout Automation (Abstract)

Nuttorn Jangkrajarng , University of Washington, Seattle, WA
C-J. Richard Shi , University of Washington, Seattle, WA
Roy Hartono , University of Washington, Seattle, WA
Sambuddha Bhattacharya , University of Washington, Seattle, WA
pp. 400-405

Multi-Level Placement with Circuit Schema Based Clustering in Analog IC Layouts (Abstract)

Takashi Nojima , SII EDA Technologies Inc., Japan; The University of Kitakyushu, Japan
Yoji Kajitani , The University of Kitakyushu, Japan
Shigetoshi Nakatake , The University of Kitakyushu, Japan
Xiaoke Zhu , SII EDA Technologies Inc., Japan
Yasuhiro Takashima , The University of Kitakyushu, Japan
pp. 406-411
Session 5A - Formal Verification

Model Checking on State Transition Diagram (Abstract)

Santanu Chattopadhyay , IIT Guwahati, India
Batsayan Das , IIT Kharagpur, India
Dipankar Sarkar , IIT Kharagpur, India
pp. 412-417

Efficient Reachability Checking using Sequential SAT (Abstract)

K.-T. Cheng , University of California - Santa Barbara
Li. C. Wang , University of California - Santa Barbara
G. Parthasarathy , University of California - Santa Barbara
M. K. Iyer , University of California - Santa Barbara
pp. 418-423

Exploiting State Encoding for Invariant Generation in Induction-Based Property Checking (Abstract)

Wolfgang Kunz , University of Kaiserslautern, Germany
Dominik Stoffel , University of Kaiserslautern, Germany
Markus Wedler , University of Kaiserslautern, Germany
pp. 424-429
Session 5B - Routing Methodology

Tradeoff Routing Resource, Runtime and Quality in Buffered Routing (Abstract)

Martin D. F. Wong , University of Illinois, Urbana, IL
Xiaoping Tang , Cadence Design Systems, San Jose, CA
pp. 430-433

Practical Methodology of Post-Layout Gate Sizing for 15% More Power Saving (Abstract)

Noriyuki Miura , Keio University, Japan
Tadahiro Kuroda , Keio University, Japan
Naoki Kato , Hitachi, Ltd., Japan
pp. 434-437

Interconnect Design Methods for Memory Design (Abstract)

Massoud Pedram , Univ. of Southern California, Los Angeles
Chanseok Hwang , Univ. of Southern California, Los Angeles
pp. 438-443

Optimal Planning for Mesh-Based Power Distribution (Abstract)

Andrew B. Kahng , UCSD CSE Department
Qinke Wang , UCSD CSE Department
Hongyu Chen , UCSD CSE Department
Makoto Mori , Fujitsu Limited
Chung-Kuan Cheng , UCSD CSE Department
pp. 444-449
Session 5C - Exploration for Advanced SoC Design

2.5D System Integration: A Design Driven System Implementation Schema (Abstract)

Wojciech Maly , Carnegie Mellon University, Pittsburgh, PA
Yangdong (Steven) Deng , Carnegie Mellon University, Pittsburgh, PA
pp. 450-455

An HMAC Processor with Integrated SHA-1 and MD5 Algorithms (Abstract)

Cheng-Wen Wu , National Tsing Hua University, Taiwan
Mao-Yin Wang , National Tsing Hua University, Taiwan
Chih-Pin Su , National Tsing Hua University, Taiwan
Chih-Tsun Huang , National Tsing Hua University, Taiwan
pp. 456-458

Design Methodology for IRA Codes (Abstract)

Norbert Wehn , University of Kaiserslautern, Germany
Frank Kienle , University of Kaiserslautern, Germany
pp. 459-462
Session 5D - Embedded Software

Embedded Software Generation from System Level Design Languages (Abstract)

Rainer D?mer , University of California, Irvine, USA
Daniel Gajski , University of California, Irvine, USA
Haobo Yu , University of California, Irvine, USA
pp. 463-468

Fast and Accurate Timed Execution of High Level Embedded Software using HW/SW Interface Simulation Model (Abstract)

Ahmed Jerraya , TIMA laboratory, Grenoble, France
Sungjoo Yoo , TIMA laboratory, Grenoble, France
Aimen Bouchhima , TIMA laboratory, Grenoble, France
pp. 469-474

Energy Efficient Code Generation Exploiting Reduced Bit-Width Instruction Set Architectures (rISA) (Abstract)

Aviral Shrivastava , University of California, Irvine
Nikil Dutt , University of California, Irvine
pp. 475-477

Memory Access Driven Storage Assignment for Variables in Embedded System Design (Abstract)

Yoonseo Choi , Korea Advanced Institute of Science and Technology, Korea
Taewhan Kim , Korea Advanced Institute of Science and Technology, Korea
pp. 478-481
Session 6A - (Special Session) Embedded Tutorial: RF Modeling and Design Methodology

MOSFET Modeling for RF-CMOS Design (Abstract)

Mitiko Miura-Mattausch , Hiroshima University, Japan
pp. 482-490

RF Design Methodologies Bridging System-IC-Module Design (Abstract)

Robert A. Mullen , Cadence Design Systems, Inc., San Jose, CA
pp. 491-498
Session 6B - Power Grid Analysis and Design

Hierarchical Random-Walk Algorithms for Power Grid Analysis (Abstract)

Sachin S. Sapatnekar , University of Minnesota, Minneapolis
Haifeng Qian , University of Minnesota, Minneapolis
pp. 499-504

A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery (Abstract)

Zhu Pan , Tsinghua University, Beijing, P.R. China
Jingjing Fu , Tsinghua University, Beijing, P.R. China
Zuying Luo , Tsinghua University, Beijing, P.R. China
Yici Cai , Tsinghua University, Beijing, P.R. China
Sheldon X.-D. Tan , University of California at Riverside, CA, USA
Xianlong Hong , Tsinghua University, Beijing, P.R. China
pp. 505-510

Large-Scale Linear Circuit Simulation with an Inversed Inductance Matrix (Abstract)

Tetsuro Kage , Semiconductor Technology Academic Center, Japan
Hiroo Masuda , Semiconductor Technology Academic Center, Japan
Chieki Mizuta , Mathematical Systems Incorporated, Japan
Jiro Iwai , Mathematical Systems Incorporated, Japan
Ken Machida , Mathematical Systems Incorporated, Japan
pp. 511-516

DEPOGIT: Dense Power-Ground Interconnect Architecture for Physical Design Integrity (Abstract)

Atsushi Kurokawa , Semiconductor Technology Academic Research Center
Tetsuro Kage , Semiconductor Technology Academic Research Center
Hiroo Masuda , Semiconductor Technology Academic Research Center
Nobuto Ono , SII EDA technologies Inc.
pp. 517-522
Session 6C - (Special Session) Presentation + Poster Disscussion: University Design Contest

Design of Real-Time VGA 3-D Image Sensor Using Mixed-Signal Techniques (PDF)

Kunihiro Asada , University of Tokyo, Japan
Makoto Ikeda , University of Tokyo, Japan
Yusuke Oike , University of Tokyo, Japan
pp. 523-524

A Bandwidth and Memory Efficient MPEG-4 Shape Encoder (PDF)

Kun-Bin Lee , National Chiao Tung University, HsinChu, Taiwan
Hao-Yun Chin , National Chiao Tung University, HsinChu, Taiwan
Hui-Cheng Hsu , National Chiao Tung University, HsinChu, Taiwan
Nelson Yen-Chung Chang , National Chiao Tung University, HsinChu, Taiwan
Chein-Wei Jen , National Chiao Tung University, HsinChu, Taiwan
pp. 525-526

A Sub-mW MPEG-4 Motion Estimation Processor Core for Mobile Video Application (PDF)

M. Miyama , Kanazawa University, Japan
K. Imamura , Kanazawa University, Japan
Y. Kuroda , Kanazawa University, Japan
H. Hashimoto , Kanazawa University, Japan
M. Yoshimoto , Kanazawa University, Japan
J. Miyakoshi , Kanazawa University, Japan
pp. 527-528

Analog LSI for Motion Detection of Approaching Object with Simple-Shape Recognition Based on Lower Animal Vision (PDF)

Kimihiro Nishio , Toyohashi University of Technology, Japan
Yuzo Furukawa , Toyohashi University of Technology, Japan
Hiroo Yonezu , Toyohashi University of Technology, Japan
Shinya Sawa , Toyohashi University of Technology, Japan
pp. 529-530

350nm CMOS Test-Chip for Architecture Verification of Real-Time QVGA Color-Video Segmentation at the 90nm Technology Node (PDF)

Yohmei Harada , Hiroshima University, Japan
Tetsushi Koide , Hiroshima University, Japan
Hans J?rgen Mattausch , Hiroshima University, Japan
Takashi Morimoto , Hiroshima University, Japan
pp. 531-532

A Low-Power Graphics LSI integrating 29Mb Embedded DRAM for Mobile Multimedia Applications (PDF)

Sungdae Choi , Korea Advanced Institute of Science and Technology, Korea
Ju-Ho Sohn , Korea Advanced Institute of Science and Technology, Korea
Hoi-Jun Yoo , Korea Advanced Institute of Science and Technology, Korea
Young-Don Bae , Korea Advanced Institute of Science and Technology, Korea
Ramchan Woo , Korea Advanced Institute of Science and Technology, Korea
Seong-Jun Song , Korea Advanced Institute of Science and Technology, Korea
pp. 533-534

A High Efficiency 0.5W BTL Class-D Audio Amplifier with RWDM Technique (PDF)

Simon C. Li , National Yunlin University of Science and Technology
Vincent Chia-Chang Lin , Etrend Electronics, Inc.
pp. 535-536

A Small-Area High-Performance 512-Point 2-Dimensional FFT Single-Chip Processor (PDF)

Kazuyuki Maruo , Advantest Laboratories Ltd., Japan
Tadahiro Ohmi , University of Tohoku, Japan
Naoto Miyamoto , University of Tohoku, Japan
Koji Kotani , University of Tohoku, Japan
Leo Karnan , University of Tohoku, Japan
pp. 537-538

Fast Adaptive DC-DC Conversion Using Dual-Loop One-Cycle Control in Standard Digital CMOS Process (PDF)

Chi-Ying Tsui , The Hong Kong University of Science & Technology, Hong Kong
Dongsheng Ma , Louisiana State University, Baton Rouge, LA
Wing-Hung Ki , The Hong Kong University of Science & Technology, Hong Kong
pp. 539-540

A Dual-Band Image-Reject Mixer for GPS with 64dB Image Rejection (PDF)

Kenji Taniguchi , Osaka University, Japan
Masaki Haruoka , Osaka University, Japan; Furuno Electric Co., Ltd, Japan
Yoshihiro Utsurogi , Osaka University, Japan
Toshimasa Matsuoka , Osaka University, Japan
pp. 541-542

A Reliable Low-Power Fast Skew-Compensation Circuit (PDF)

Yi-Ming Wang , Chung-Cheng University, Taiwan
Jinn-Shyan Wang , Chung-Cheng University, Taiwan
pp. 547-548

A Retinal Prosthetic Device using a Pulse-Frequency-Modulation CMOS Image Sensor (PDF)

Masahiro Nunoshita , NAIST, Japan
Keiichiro Kagawa , NAIST, Japan
Tetsuo Furumiya , NAIST, Japan
Takashi Tokuda , NAIST, Japan
Jun Ohta , Nara Institute of Science and Technology (NAIST)
Akihiro Uehara , NAIST, Japan
David C. Ng , NAIST, Japan
pp. 549-550

Compact 12-Port Multi-Bank Register File Test-Chip in 0.35μm CMOS for Highly Parallel Processors (PDF)

Tetsushi Koide , Hiroshima University, Japan
Tetsuya Sueyoshi , Hiroshima University, Japan
Yosuke Mitani , Hiroshima City University, Japan
Tetsuo Hironaka , Hiroshima City University, Japan
Hiroshi Uchida , Hiroshima University, Japan
Hans J?rgen Mattausch , Hiroshima University, Japan
pp. 551-552

A Low Power Asynchronous Java Processor for Contactless Smart Card (PDF)

Cheong-Fat Chan , CUHK, Hong Kong
Hao Min , Fudan University, P.R. China
Chun-Pong Yu , CUHK, Hong Kong
Kong-Pang Pun , CUHK, Hong Kong
Chiu-Sing Choy , CUHK, Hong Kong
pp. 553-554

An Image-Sensor-Based Optical Receiver Fabricated in a Standard 0.35-μm CMOS Technology for Free-Space Optical Communications (PDF)

Tomoaki Kawakami , Nara Institute of Science and Technology, Japan
Akiko Fujiuchi , Nara Institute of Science and Technology, Japan
Takashi Ikeuchi , Nara Institute of Science and Technology, Japan
Masahiro Nunoshita , Nara Institute of Science and Technology, Japan
Jun Ohta , Nara Institute of Science and Technology, Japan
Keiichiro Kagawa , Nara Institute of Science and Technology, Japan
Hiroaki Asazu , Nara Institute of Science and Technology, Japan
pp. 555-556

The Flexible Processor An Approach for Single-Chip Hardware Emulation by Dynamic Reconfiguration (PDF)

Koji Kotani , Tohoku University, Japan
Masanori Fujibayashi , Tohoku University, Japan
Karnan Leo , Tohoku University, Japan
Takeshi Ohkawa , Tohoku University, Japan
Naoto Miyamoto , Tohoku University, Japan
Toshiyuki Nozawa , Tohoku University, Japan
Tadahiro Ohmi , Tohoku University, Japan
Soichiro Kita , Tohoku University, Japan
pp. 557-558

A VDD and Temperature Independent CMOS Voltage Reference Circuit (PDF)

T. Matsuda , Toyama Prefectural University, Japan
S. Yamamoto , Shikino Hightech Co., Ltd., Japan
A. Kanamori , Toyama Prefectural University, Japan
S. Nakajima , Shikino Hightech Co., Ltd.
R. Minami , Toyama Prefectural University, Japan
H. Iwata , Toyama Prefectural University, Japan
T. Ihara , Shikino Hightech Co., Ltd.
T. Ohzone , Okayama Prefectural University, Japan
pp. 559-560

A Dual-Band Switching Digital Controller for a Buck Converter (PDF)

Wing-Hung Ki , The Hong Kong University of Science and Technology, China
Chi-Ying Tsui , The Hong Kong University of Science and Technology, China
Martin Yeung-Kei Chui , The Hong Kong University of Science and Technology, China
pp. 561-562

Golay and Wavelet Error Control Codes in VLSI (PDF)

Vincent J. Mooney III , Georgia Institute of Technology, Atlanta, GA
Arunkumar Balasundaram , Georgia Institute of Technology, Atlanta, GA
Jun Cheol Park , Georgia Institute of Technology, Atlanta, GA
Angelo Pereira , Georgia Institute of Technology, Atlanta, GA
pp. 563-564

Timing Measurement Unit with Multi-Stage TVC for Embedded Memories (PDF)

Tsin-Yuan Chang , National Tsing-Hua University, Taiwan
Shao-Sheng Yang , National Tsing-Hua University, Taiwan
Kae-Jiun Mo , National Tsing-Hua University, Taiwan
pp. 565-566

Development of a Waveform Sampling Front-End ASIC for PET (PDF)

J. Y. Yeom , University of Tokyo, Japan
T. Ishitsu , University of Tokyo, Japan
H. Takahashi , University of Tokyo, Japan
pp. 567-568

A Dynamic Element Matching Circuit for Multi-Bit Delta-Sigma Modulators (PDF)

Takao Waho , Sophia University, Japan
Shin-ya Kobayashi , Sophia University, Japan
Ryozo Katoh , Sophia University, Japan
pp. 569-570

Design of POP-11 (PDP-11 on Programmable chip) (PDF)

Naohiko Shimizu , Tokai University, Japan
Yoshihiro Iida , Tokai University, Japan
pp. 571-572

A Closed Caption TV Microcontroller (PDF)

Ekachai Leelarasmee , Chulalongkorn University, Thailand
Kanitpong Pengwon , Chiang Mai University, Thailand
pp. 573-574

Improvement of Saturation Characteristics of a Frequency-Demodulation CMOS Image Sensor (PDF)

Jun Ohta , Nara Institute of Science and Technology (NAIST), Japan
Koichi Yamamoto , Nara Institute of Science and Technology (NAIST), Japan
Yu Oya , Nara Institute of Science and Technology (NAIST), Japan
Masahiro Nunoshita , Nara Institute of Science and Technology (NAIST), Japan
Takashi Tokuda , Nara Institute of Science and Technology (NAIST), Japan
Keiichiro Kagawa , Nara Institute of Science and Technology (NAIST), Japan
pp. 575-576

Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA (PDF)

Hala A. Farouk , Arab Academy for Science, Egypt
Magdy Saeb , Arab Academy for Science, Egypt
pp. 577-578
Session 6D - Novel Techniques in Logic Synthesis

Preserving Synchronizing Sequences of Sequential Circuits After Retiming (Abstract)

Karem A. Sakallah , University of Michigan
John Moondanos , Intel Corporation
Maher N. Mneimneh , University of Michigan
pp. 579-584

A Fast Method to Derive Minimum SOPs for Decomposable Functions (Abstract)

Jon T. Butler , Naval Postgraduate School, Monterey, CA
Tsutomu Sasao , Kyushu Institute of Technology, Japan
pp. 585-590

Efficient Computation of Canonical Form for Boolean Matching in Large Libraries (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Debatosh Debnath , Oakland University, Rochester, Michigan
pp. 591-596

Disjoint-Support Boolean Decomposition Combining Functional and Structural Methods (Abstract)

Andr? Martinelli , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
Ren? Krenz , Royal Institute of Technology, IMIT/KTH, Stockholm, Sweden
pp. 597-599

Transduction Method for Design of Logic Cell Structure (Abstract)

Katsunori Tanaka , Kyoto University, Japan
Yahiko Kambayashi , Kyoto University, Japan
pp. 600-603
Session 7A - (Special Session) Invited Talks: Future of ITS Technologies in the Ubiquitous Society
Session 7B - Buffer Planning

Complexity Analysis and Speedup Techniques for Optimal Buffer Insertion with Minimum Cost (Abstract)

Zhuo Li , Texas A&M University, College Station, TX
Weiping Shi , Texas A&M University, College Station, TX
Charles J. Alpert , IBM Austin Research Lab., Austin, TX
pp. 609-614

A Buffer Planning Algorithm with Congestion Optimization (Abstract)

Jun Gu , Science & Technology University of Hong Kong
Sheqin Dong , Tsinghua Univ., Beijing, China
Xianlong Hong , Tsinghua Univ., Beijing, China
Yici Cai , Tsinghua Univ., Beijing, China
Song Chen , Tsinghua Univ., Beijing, China
Chung-Kuan Cheng , Univ. of California, San Diego USA
Yuchun Ma , Tsinghua Univ., Beijing, China
pp. 615-620

Buffer Allocation Algorithm with Consideration of Routing Congestion (Abstract)

Yici Cai , Tsinghua University, Beijing, China
Jun Gu , Science & Technology University of HongKong, Hong Kong
Sheqin Dong , Tsinghua University, Beijing, China
Song Chen , Tsinghua University, Beijing, China
Yuchun Ma , Tsinghua University, Beijing, China
Xianlong Hong , Tsinghua University, Beijing, China
Chung-Kuan Cheng , University of California, San Diego
pp. 621-623

Integrating Buffer Planning with Floorplanning for Simultaneous Multi-Objective Optimization (Abstract)

Yi-Hui Cheng , Synopsys Inc., Taipei, Taiwan
Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
pp. 624-627
Session 7C - Design Verification and Simulation

Verification of Timed Circuits with Symbolic Delays (Abstract)

Robert Claris? , Universitat Polit?cnica de Catalunya
Jordi Cortadella , Universitat Polit?cnica de Catalunya
pp. 628-633

Improved Symbolic Simulation By Functional-Space Decomposition (Abstract)

Kwang-Ting Cheng , UC-Santa Barbara
Li-C. Wang , UC-Santa Barbara
Tao Feng , UC-Santa Barbara
pp. 634-639

Improving Simulation-Based Verification by Means of Formal Methods (Abstract)

G?rschwin Fey , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 640-643

Parallel Verilog Simulation: Architecture and Circuit Partition (Abstract)

Yang Guo , National University of Defense Technology, P. R. China
FuJiang Ao , National University of Defense Technology, P. R. China
Tun Li , National University of Defense Technology, P. R. China
SiKun Li , National University of Defense Technology, P. R. China
GongJie Liu , National University of Defense Technology, P. R. China
pp. 644-646
Session 7D - Task Scheduling with DVS

Minimizing Energy Consumption of Multiple-Processors-Core Systems with Simultaneous Task Allocation, Scheduling and Voltage Assignment (Abstract)

Wing-Hung Ki , Hong Kong University of Science and Technology, China
Lap-Fai Leung , Hong Kong University of Science and Technology, China
Chi-Ying Tsui , Hong Kong University of Science and Technology, China
pp. 647-652

Dynamic Voltage Scaling of Periodic and Aperiodic Tasks in Priority-Driven Systems (Abstract)

Jihong Kim , Seoul National University, Korea
Dongkun Shin , Seoul National University, Korea
pp. 653-658

Fast and Efficient Voltage Scheduling by Evolutionary Slack Distribution (Abstract)

Nader Bagherzadeh , University of California, Irvine
Pai Chou , University of California, Irvine
Bita Gorji-Ara , University of California, Irvine
David Jensen , Rockwell Collins, Cedar Rapids, IA
Mehrdad Reshadi , University of California, Irvine
pp. 659-662

Minimizing Energy Consumption of Hard Real-Time Systems with Simultaneous Tasks Scheduling and Voltage Assignment Using Statistical Data (Abstract)

Wing-Hung Ki , Hong Kong University of Science and Technology
Lap-Fai Leung , Hong Kong University of Science and Technology
Chi-Ying Tsui , Hong Kong University of Science and Technology
pp. 663-665
Session 8A - Global Routing

A Fast Congestion Estimator for Routing with Bounded Detours (Abstract)

Lerong Cheng , University of Colorado at Boulder
Xiaoyu Song , Portland State University, OR
Guowu Yang , Portland State University, OR
Zhiwei Tang , Portland State University, OR
pp. 666-670

Accurate and Efficient Flow based Congestion Estimation in Floorplanning (Abstract)

Chris C. N. Chu , Iowa State University, Ames
Zion Cien Shen , Iowa State University, Ames
pp. 671-676

A Coupling and Crosstalk Considered Timing-Driven Global Routing Algorithm for High Performance Circuit Design (Abstract)

Xianlong Hong , Tsinghua Univ., Beijing, P.R. China
Jingyu Xu , Tsinghua Univ., Beijing, P.R. China
Tong Jing , Tsinghua Univ., Beijing, P.R. China
Ling Zhang , Tsinghua Univ., Beijing, P.R. China
Jun Gu , Hong Kong Univ. of S & T, P. R. China
pp. 677-682

Timing-Constrained Congestion-Driven Global Routing (Abstract)

Shun-Hua Lin , Chung-Hua University, Hsinchu, Taiwan
Jin-Tai Yan , Chung-Hua University, Hsinchu, Taiwan
pp. 683-686

Efficient Octilinear Steiner Tree Construction Based on Spanning Graphs (Abstract)

Xianlong Hong , Tsinghua Univ., Beijing, P. R. China
Tong Jing , Tsinghua Univ., Beijing, P. R. China
Hai Zhou , Northwestern Univ., Evanston, IL
Qi Zhu , Tsinghua Univ., Beijing, P. R. China; UC Berkeley, CA
Yang Yang , Tsinghua Univ., Beijing, P. R. China
pp. 687-690
Session 8B - Interconnect and ESD Extraction

Representative Frequency for Interconnect R(f)L(f)C Extraction (Abstract)

Masanori Hashimoto , Kyoto University, Japan
Akira Tsuchiya , Kyoto University, Japan
Hidetoshi Onodera , Kyoto University, Japan
pp. 691-696

A Mixed-Mode Extraction Flow for High Performance Microprocessors (Abstract)

Eric Pettus , Motorola Inc., Austin, TX
Tao Jiang , Motorola Inc., Austin, TX
Daksh Lehther , Motorola Inc., Austin, TX
pp. 697-701

An Efficient Method MEGCR for Solving Systems with Multiple Right-Hand Sides in 3-D Parasitic Inductance Extraction (Abstract)

Zeyi Wang , Tsinghua Univ., Beijing, China
Liu Yang , Tsinghua Univ., Beijing, China
Xiaobo Guo , Tsinghua Univ., Beijing, China
pp. 702-706

Fast and Accurate Extraction of 3-D Interconnect Resistance: Improved Quasi-Multiple Medium Accelerated BEM Method (Abstract)

Xiren Wang , Tsinghua Univ., Beijing, P.R. China
Zeyi Wang , Tsinghua Univ., Beijing, P.R. China
Deyan Liu , UCSC, Santa Cruz, CA
Wenjian Yu , Tsinghua Univ., Beijing, P.R. China
pp. 707-709

Concept and Extraction Method of ESD-Critical Parameters for Function-Based Layout-Level ESD Protection Circuit Design Verification (Abstract)

R. Y. Zhan , Illinois Institute of Technology, Chicago, IL
H. G. Feng , Illinois Institute of Technology, Chicago, IL
X. K. Guan , Illinois Institute of Technology, Chicago, IL
Q. Wu , Illinois Institute of Technology, Chicago, IL
A. Z. Wang , Illinois Institute of Technology, Chicago, IL
G. Chen , Illinois Institute of Technology, Chicago, IL
H. L. Xie , Illinois Institute of Technology, Chicago, IL
pp. 710-712
Session 8C - Reconfigurable Systems

Interconnect Capacitance Estimation for FPGAs (Abstract)

Jason H. Anderson , University of Toronto, Canada
Farid N. Najm , University of Toronto, Canada
pp. 713-718

Area-Minimal Algorithm for LUT-Based FPGA Technology Mapping with Duplication-Free Restriction (Abstract)

Chi-Chou Kao , National Pingtung Institute of Commerce, Pingtung, Taiwan
Yen-Tai Lai , National Cheng Kung University, Tainan, Taiwan
pp. 719-724

Temporal Floorplanning Using 3D-subTCG (Abstract)

Yao-Wen Chang , National Taiwan University, Taipei, Taiwan
Ping-Hung Yuh , National Taiwan University, Taipei, Taiwan
Chia-Lin Yang , National Taiwan University, Taipei, Taiwan
pp. 725-730

ReCSiP: A ReConfigurable Cell SImulation Platform - Accelerating Biological Applications with FPGA (Abstract)

Hideharu Amano , Keio University, Japan
Tomonori Fukushima , Keio University, Japan
Yasunori Osana , Keio University, Japan
pp. 731-733

SmartGlue: An Interface Controller with Auto Reconfiguration for Field Programmable Computing Machine (Abstract)

Bong-Il Park , Dynalith Systems, Korea
Chong-Min Kyung , Korea Advanced Institute of Science and Technology, Korea
Jae-Gon Lee , Korea Advanced Institute of Science and Technology, Korea
Young-Il Kim , Korea Advanced Institute of Science and Technology, Korea
pp. 734-736
Session 8D - HW/SW Co-Design

An SoC Architecture and its Design Methodology using Unifunctional Heterogeneous Processor Array (Abstract)

Hidetoshi Onodera , Kyoto University, Japan
Kazutoshi Kobayashi , The University of Tokyo, Japan
Masao Aramoto , Kyoto University, Japan
Yoichi Yuyama , Kyoto University, Japan
pp. 737-742

Instruction Set and Functional Unit Synthesis for SIMD Processor Cores (Abstract)

Koichi Tachikake , Waseda University, Japan
Yuichiro Miyaoka , Waseda University, Japan
Nozomu Togawa , The University of Kitakyushu, Japan; Waseda University, Japan
Masao Yanagisawa , Waseda University, Japan
Tatsuo Ohtsuki , Waseda University, Japan
pp. 743-750

A High Performance Bus Communication Architecture through Bus Splitting (Abstract)

Cheng-Kok Koh , Purdue University, West Lafayette, IN
Ruibing Lu , Purdue University, West Lafayette, IN
pp. 751-755

Automatic Generation of Bus Functional Models from Transaction level Models (Abstract)

Daniel D. Gajski , University of California, Irvine
Dongwan Shin , University of California, Irvine
Samar Abdi , University of California, Irvine
pp. 756-758

A Global Bus Power Optimization Methodology for Physical Design of Memory Dominated Systems by Coupling Bus Segmentation and Activity Driven Block Placement (Abstract)

Antonis Papanikolaou , IMEC, Leuven, Belgium
Miguel Miranda , IMEC, Leuven, Belgium
Francky Catthoor , Katholieke Universiteit Leuven, Belgium
Hua Wang , Katholieke Universiteit Leuven, Belgium
pp. 759-761
Session 9A - (Special Session) Embedded Tutorial: DFM in Nm-Process Generation

Physical CAD Changes to Incorporate Design for Lithography and Manufacturability (Abstract)

Louis K. Scheffer , Cadence Design Systems, Inc., San Jose, California
pp. 768-773
Session 9B - Advanced Interconnect Analysis

Parametric Reduced Order Modeling for Interconnect Analysis (Abstract)

C.-J. Richard Shi , University of Washington, Seattle
Guoyong Shi , University of Washington, Seattle
pp. 774-779

Realizable Parasitic Reduction For Distributed Interconnects Using Matrix Pencil Technique (Abstract)

Janet Wang , University of Arizona
Omar Hafiz , University of Arizona
Xing Wang , University of Arizona
Prashant Saxena , STL Strategy CAD Lab, Intel Corporation
pp. 780-785

SPICE Compatible Circuit Models for Partial Reluctance K (Abstract)

Wayne Dai , UC Santa Cruz, CA
Hao Ji , UC Santa Cruz, CA
Qingjian Yu , Cadence Design Systems, Inc., San Jose, CA
pp. 786-791

Frequency-Dependent Reluctance Extraction (Abstract)

Charlie C.-P. Chen , National Taiwan University
Tsung-Hao Chen , University of Wisconsin-Madison
Clement Luk , Optimal corporation
pp. 792-797
Session 9C - (Special Session) Panel Discussion: Future Reconfigurable Computing System
Session 9D - System-Level Architecture

Enabling On-Chip Diversity Through Architectural Communication Design (Abstract)

Tudor Dumitras , Carnegie Mellon University, Pittsburgh, PA
Sam Kerner , Carnegie Mellon University, Pittsburgh, PA
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 799-805

A Novel Memory Size Model for Variable-Mapping In System Level Design (Abstract)

Haobo Yu , University of California, Irvine
Lukai Cai , University of California, Irvine
Daniel Gajski , University of California, Irvine
pp. 812-817

A Compressed Frame Buffer to Reduce Display Power Consumption in Mobile Systems (Abstract)

Massoud Pedram , University of Southern California
Naehyuck Chang , Seoul National University, Korea
Hojun Shim , Seoul National University, Korea
pp. 818-823
Session 10A - Embedded System Architectures

Instruction Buffering Exploration for Low Energy VLIWs with Instruction Clusters (Abstract)

Henk Corporaal , TU Eindhoven, Netherlands
Francisco Barat , K.U. Leuven/ESAT, Belgium
Francky Catthoor , IMEC vzw, Belgium
Murali Jayapala , K.U. Leuven/ESAT, Belgium
Rudy Lauwereins , IMEC vzw, Belgium
Tom Vander Aa , K.U. Leuven/ESAT, Belgium
Geert Deconinck , K.U. Leuven/ESAT, Belgium
pp. 824-829

A Static and Dynamic Energy Reduction Technique for I-Cache and BTB in Embedded Processors (Abstract)

Toshinori Sato , Kyushu Institute of Technology, Japan; PRESTO, Japan
Hidenori Sato , Kyushu Institute of Technology, Japan
pp. 830-833

Resource-Constrained Low-Power Bus Encoding with Crosstalk Delay Elimination (Abstract)

Chun-Gi Lyuh , Korea Advanced Institute of Science and Technology, KOREA
Taewhan Kim , Korea Advanced Institute of Science and Technology, KOREA
Meeyoung Cha , Korea Advanced Institute of Science and Technology, KOREA
pp. 834-837

Compiler based Exploration of DSP Energy Savings by SIMD Operations (Abstract)

Gerhard Fettweis , Technische Universit?t Dresden, Germany
Peter Marwedel , University of Dortmund, Germany
Markus Lorenz , University of Dortmund, Germany
Rainer Leupers , Aachen University of Technology, Germany
Thorsten Dr?ger , Technische Universit?t Dresden, Germany
pp. 838-841

Synthesizable HDL Generation Method for Configurable VLIW Processors (Abstract)

Masaharu Imai , Osaka University, Japan
Keishi Sakanushi , Osaka University, Japan
Yoshinori Takeuchi , Osaka University, Japan
Koji Okuda , Osaka University, Japan
Yuki Kobayashi , Osaka University, Japan
Shinsuke Kobayashi , Osaka University, Japan
pp. 842-845
Session 10B - Crosstalk Noise Analysis

A Non-Iterative Model for Switching Window Computation with Crosstalk Noise (Abstract)

Janet Meiling Wang , University of Arizona at Tucson
Pinhong Chen , Cadence Corperation
Omar Hafiz , University of Arizona at Tucson
pp. 846-851

Gate Delay Calculation Considering the Crosstalk Capacitances (Abstract)

Massoud Pedram , University of Southern California
Soroush Abbaspour , University of Southern California
pp. 852-857

A Simplified Transmission-Line Based Crosstalk Noise Model for On-Chip RLC Wiring (Abstract)

Kanak Agarwal , University of Michigan
David Blaauw , University of Michigan
Dennis Sylvester , University of Michigan
pp. 858-864
Session 10C - Expressions for Boolean Functions

Minimization of the Expected Path Length in BDDs Based on Local Changes (Abstract)

Wolfgang G?nther , Infineon Technologies, Germany
Rolf Drechsler , University of Bremen, Germany
R?diger Ebendt , University of Bremen, Germany
pp. 865-870

Minimization of Memory Size for Heterogeneous MDDs (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology
Shinobu Nagayama , Kyushu Institute of Technology
pp. 871-874

Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization (Abstract)

Wolfgang G?nther , Infineon Technologies, Germany
R?diger Ebendt , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 875-878

Satisfiability and Integer Programming As Complementary Tools (Abstract)

Dian Zhou , The University of Texas at Dallas
Ruiming Li , The University of Texas at Dallas
Donglei Du , University of New Brunswick
pp. 879-882

ShatterPB: Symmetry-Breaking for Pseudo-Boolean Formulas (Abstract)

Igor L. Markov , University of Michigan, Ann Arbor
Arathi Ramani , University of Michigan, Ann Arbor
Karem A. Sakallah , University of Michigan, Ann Arbor
Fadi A. Aloul , American University in Dubai
pp. 883-886
Session 10D - Semi-Custom Techniques in System Design

Automatic Process Migration of Datapath Hard IP Libraries (Abstract)

Fang Fang , University of Toronto, Canada
Jianwen Zhu , University of Toronto, Canada
pp. 887-892

Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN
Cheng-Kok Koh , Purdue University, West Lafayette, IN
Yiran Chen , Purdue University, West Lafayette, IN
pp. 893-898

High-Level Area and Power-Up Current Estimation Considering Rich Cell Library (Abstract)

Rakesh J. Patel , Intel Corporation, Santa Clara, CA
Joseph M. Basile , Intel Corporation, Santa Clara, CA
Fei Li , University of California, Los Angeles, CA
Lei He , University of California, Los Angeles, CA
Hema Ramamurthy , Intel Corporation, Santa Clara, CA
pp. 899-904

Author Index (PDF)

pp. 905-911
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