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Asia and South Pacific Design Automation Conference (2004)
Pacifico Yokohama, Yokohama, Japan
Jan. 27, 2004 to Jan. 30, 2004
ISBN: 0-7803-8175-0
pp: 824-829
Tom Vander Aa , K.U. Leuven/ESAT, Belgium
Murali Jayapala , K.U. Leuven/ESAT, Belgium
Francisco Barat , K.U. Leuven/ESAT, Belgium
Geert Deconinck , K.U. Leuven/ESAT, Belgium
Rudy Lauwereins , IMEC vzw, Belgium
Francky Catthoor , IMEC vzw, Belgium
Henk Corporaal , TU Eindhoven, Netherlands
For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled clustered loop buffers are energy efficient. However current compilers for VLIW do not fully exploit the potentials offered by such a clustered organization This paper presents an algorithm to explore what is the optimal loop buffer configuration and the optimal way to use this configuration for an application or a set of applications. Results for the MediaBench application suite show an additional 18% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional non-clustered approaches to the loop buffer without compromising performance.

H. Corporaal et al., "Instruction Buffering Exploration for Low Energy VLIWs with Instruction Clusters," Asia and South Pacific Design Automation Conference(ASP-DAC), Pacifico Yokohama, Yokohama, Japan, 2004, pp. 824-829.
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