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Asia and South Pacific Design Automation Conference (2004)
Pacifico Yokohama, Yokohama, Japan
Jan. 27, 2004 to Jan. 30, 2004
ISBN: 0-7803-8175-0
pp: 628-633
Robert Claris? , Universitat Polit?cnica de Catalunya
Jordi Cortadella , Universitat Polit?cnica de Catalunya
ABSTRACT
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicability of the approach.
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CITATION

R. Claris? and J. Cortadella, "Verification of Timed Circuits with Symbolic Delays," Asia and South Pacific Design Automation Conference(ASP-DAC), Pacifico Yokohama, Yokohama, Japan, 2004, pp. 628-633.
doi:10.1109/ASPDAC.2004.208
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